453 lines
12 KiB
C
453 lines
12 KiB
C
/*
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* Broadcom NetXtreme-E RoCE driver.
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*
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* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
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* Broadcom refers to Broadcom Limited and/or its subsidiaries.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Description: QPLib resource manager (header)
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*/
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#ifndef __BNXT_QPLIB_RES_H__
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#define __BNXT_QPLIB_RES_H__
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extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
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#define CHIP_NUM_57508 0x1750
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#define CHIP_NUM_57504 0x1751
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#define CHIP_NUM_57502 0x1752
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struct bnxt_qplib_drv_modes {
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u8 wqe_mode;
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/* Other modes to follow here */
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};
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struct bnxt_qplib_chip_ctx {
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u16 chip_num;
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u8 chip_rev;
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u8 chip_metal;
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u16 hw_stats_size;
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struct bnxt_qplib_drv_modes modes;
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};
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#define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *))
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#define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1)
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#define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
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#define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG)
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#define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1))
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#define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \
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((HWQ_CMP(hwq->prod, hwq)\
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- HWQ_CMP(hwq->cons, hwq))\
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& (hwq->max_elements - 1)))
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enum bnxt_qplib_hwq_type {
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HWQ_TYPE_CTX,
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HWQ_TYPE_QUEUE,
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HWQ_TYPE_L2_CMPL,
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HWQ_TYPE_MR
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};
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#define MAX_PBL_LVL_0_PGS 1
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#define MAX_PBL_LVL_1_PGS 512
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#define MAX_PBL_LVL_1_PGS_SHIFT 9
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#define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
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#define MAX_PBL_LVL_2_PGS (256 * 512)
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#define MAX_PDL_LVL_SHIFT 9
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enum bnxt_qplib_pbl_lvl {
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PBL_LVL_0,
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PBL_LVL_1,
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PBL_LVL_2,
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PBL_LVL_MAX
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};
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#define ROCE_PG_SIZE_4K (4 * 1024)
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#define ROCE_PG_SIZE_8K (8 * 1024)
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#define ROCE_PG_SIZE_64K (64 * 1024)
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#define ROCE_PG_SIZE_2M (2 * 1024 * 1024)
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#define ROCE_PG_SIZE_8M (8 * 1024 * 1024)
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#define ROCE_PG_SIZE_1G (1024 * 1024 * 1024)
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enum bnxt_qplib_hwrm_pg_size {
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BNXT_QPLIB_HWRM_PG_SIZE_4K = 0,
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BNXT_QPLIB_HWRM_PG_SIZE_8K = 1,
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BNXT_QPLIB_HWRM_PG_SIZE_64K = 2,
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BNXT_QPLIB_HWRM_PG_SIZE_2M = 3,
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BNXT_QPLIB_HWRM_PG_SIZE_8M = 4,
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BNXT_QPLIB_HWRM_PG_SIZE_1G = 5,
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};
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struct bnxt_qplib_reg_desc {
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u8 bar_id;
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resource_size_t bar_base;
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void __iomem *bar_reg;
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size_t len;
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};
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struct bnxt_qplib_pbl {
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u32 pg_count;
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u32 pg_size;
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void **pg_arr;
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dma_addr_t *pg_map_arr;
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};
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struct bnxt_qplib_sg_info {
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struct ib_umem *umem;
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u32 npages;
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u32 pgshft;
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u32 pgsize;
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bool nopte;
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};
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struct bnxt_qplib_hwq_attr {
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struct bnxt_qplib_res *res;
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struct bnxt_qplib_sg_info *sginfo;
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enum bnxt_qplib_hwq_type type;
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u32 depth;
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u32 stride;
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u32 aux_stride;
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u32 aux_depth;
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};
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struct bnxt_qplib_hwq {
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struct pci_dev *pdev;
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/* lock to protect qplib_hwq */
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spinlock_t lock;
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struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1];
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enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */
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/* ptr for easy access to the PBL entries */
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void **pbl_ptr;
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/* ptr for easy access to the dma_addr */
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dma_addr_t *pbl_dma_ptr;
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u32 max_elements;
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u32 depth;
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u16 element_size; /* Size of each entry */
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u16 qe_ppg; /* queue entry per page */
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u32 prod; /* raw */
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u32 cons; /* raw */
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u8 cp_bit;
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u8 is_user;
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u64 *pad_pg;
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u32 pad_stride;
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u32 pad_pgofft;
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};
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struct bnxt_qplib_db_info {
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void __iomem *db;
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void __iomem *priv_db;
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struct bnxt_qplib_hwq *hwq;
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u32 xid;
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u32 max_slot;
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};
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/* Tables */
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struct bnxt_qplib_pd_tbl {
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unsigned long *tbl;
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u32 max;
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};
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struct bnxt_qplib_sgid_tbl {
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struct bnxt_qplib_gid_info *tbl;
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u16 *hw_id;
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u16 max;
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u16 active;
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void *ctx;
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u8 *vlan;
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};
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struct bnxt_qplib_dpi {
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u32 dpi;
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void __iomem *dbr;
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u64 umdbr;
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};
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struct bnxt_qplib_dpi_tbl {
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void **app_tbl;
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unsigned long *tbl;
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u16 max;
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void __iomem *dbr_bar_reg_iomem;
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u64 unmapped_dbr;
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};
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struct bnxt_qplib_stats {
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dma_addr_t dma_map;
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void *dma;
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u32 size;
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u32 fw_id;
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};
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struct bnxt_qplib_vf_res {
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u32 max_qp_per_vf;
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u32 max_mrw_per_vf;
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u32 max_srq_per_vf;
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u32 max_cq_per_vf;
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u32 max_gid_per_vf;
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};
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#define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448
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#define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64
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#define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64
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#define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128
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#define MAX_TQM_ALLOC_REQ 48
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#define MAX_TQM_ALLOC_BLK_SIZE 8
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struct bnxt_qplib_tqm_ctx {
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struct bnxt_qplib_hwq pde;
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u8 pde_level; /* Original level */
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struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ];
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u8 qcount[MAX_TQM_ALLOC_REQ];
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};
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struct bnxt_qplib_ctx {
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u32 qpc_count;
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struct bnxt_qplib_hwq qpc_tbl;
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u32 mrw_count;
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struct bnxt_qplib_hwq mrw_tbl;
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u32 srqc_count;
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struct bnxt_qplib_hwq srqc_tbl;
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u32 cq_count;
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struct bnxt_qplib_hwq cq_tbl;
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struct bnxt_qplib_hwq tim_tbl;
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struct bnxt_qplib_tqm_ctx tqm_ctx;
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struct bnxt_qplib_stats stats;
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struct bnxt_qplib_vf_res vf_res;
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u64 hwrm_intf_ver;
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};
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struct bnxt_qplib_res {
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struct pci_dev *pdev;
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struct bnxt_qplib_chip_ctx *cctx;
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struct bnxt_qplib_dev_attr *dattr;
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struct net_device *netdev;
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struct bnxt_qplib_rcfw *rcfw;
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struct bnxt_qplib_pd_tbl pd_tbl;
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struct bnxt_qplib_sgid_tbl sgid_tbl;
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struct bnxt_qplib_dpi_tbl dpi_tbl;
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bool prio;
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bool is_vf;
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};
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static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
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{
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return (cctx->chip_num == CHIP_NUM_57508 ||
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cctx->chip_num == CHIP_NUM_57504 ||
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cctx->chip_num == CHIP_NUM_57502);
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}
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static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
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{
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return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
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HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
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}
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static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
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{
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return bnxt_qplib_is_chip_gen_p5(cctx) ?
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RING_ALLOC_REQ_RING_TYPE_NQ :
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RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
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}
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static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
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{
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u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
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struct bnxt_qplib_pbl *pbl;
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pbl = &hwq->pbl[PBL_LVL_0];
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switch (pbl->pg_size) {
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case ROCE_PG_SIZE_4K:
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pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
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break;
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case ROCE_PG_SIZE_8K:
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pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
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break;
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case ROCE_PG_SIZE_64K:
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pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
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break;
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case ROCE_PG_SIZE_2M:
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pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
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break;
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case ROCE_PG_SIZE_8M:
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pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
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break;
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case ROCE_PG_SIZE_1G:
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pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
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break;
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default:
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break;
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}
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return pg_size;
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}
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static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
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u32 indx, u64 *pg)
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{
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u32 pg_num, pg_idx;
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pg_num = (indx / hwq->qe_ppg);
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pg_idx = (indx % hwq->qe_ppg);
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if (pg)
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*pg = (u64)&hwq->pbl_ptr[pg_num];
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return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
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}
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static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
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{
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idx += hwq->prod;
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if (idx >= hwq->depth)
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idx -= hwq->depth;
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return bnxt_qplib_get_qe(hwq, idx, NULL);
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}
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#define to_bnxt_qplib(ptr, type, member) \
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container_of(ptr, type, member)
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struct bnxt_qplib_pd;
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struct bnxt_qplib_dev_attr;
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void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
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struct bnxt_qplib_hwq *hwq);
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int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
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struct bnxt_qplib_hwq_attr *hwq_attr);
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int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
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struct bnxt_qplib_pd *pd);
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int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
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struct bnxt_qplib_pd_tbl *pd_tbl,
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struct bnxt_qplib_pd *pd);
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int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
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struct bnxt_qplib_dpi *dpi,
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void *app);
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int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
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struct bnxt_qplib_dpi_tbl *dpi_tbl,
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struct bnxt_qplib_dpi *dpi);
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void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
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int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
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void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
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int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
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struct net_device *netdev,
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struct bnxt_qplib_dev_attr *dev_attr);
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void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
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struct bnxt_qplib_ctx *ctx);
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int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
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struct bnxt_qplib_ctx *ctx,
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bool virt_fn, bool is_p5);
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int bnxt_qplib_determine_atomics(struct pci_dev *dev);
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static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
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{
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hwq->prod = (hwq->prod + cnt) % hwq->depth;
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}
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static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
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u32 cnt)
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{
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hwq->cons = (hwq->cons + cnt) % hwq->depth;
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}
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static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
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bool arm)
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{
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u32 key;
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key = info->hwq->cons & (info->hwq->max_elements - 1);
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key |= (CMPL_DOORBELL_IDX_VALID |
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(CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
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if (!arm)
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key |= CMPL_DOORBELL_MASK;
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writel(key, info->db);
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}
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static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
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u32 type)
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{
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u64 key = 0;
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key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
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key <<= 32;
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key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
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DBC_DBC_INDEX_MASK;
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writeq(key, info->db);
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}
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static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
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u32 type)
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{
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u64 key = 0;
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key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
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key <<= 32;
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key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
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writeq(key, info->db);
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}
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static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
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u32 type)
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{
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u64 key = 0;
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key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
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key <<= 32;
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writeq(key, info->priv_db);
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}
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static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
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u32 th)
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{
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u64 key = 0;
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key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
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key <<= 32;
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key |= th & DBC_DBC_INDEX_MASK;
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writeq(key, info->priv_db);
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}
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static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
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struct bnxt_qplib_chip_ctx *cctx,
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bool arm)
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{
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u32 type;
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type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
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if (bnxt_qplib_is_chip_gen_p5(cctx))
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bnxt_qplib_ring_db(info, type);
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else
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bnxt_qplib_ring_db32(info, arm);
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}
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static inline bool _is_ext_stats_supported(u16 dev_cap_flags)
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{
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return dev_cap_flags &
|
|
CREQ_QUERY_FUNC_RESP_SB_EXT_STATS;
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}
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#endif /* __BNXT_QPLIB_RES_H__ */
|