151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
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/* Copyright (c) 2017 - 2021 Intel Corporation */
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#include "osdep.h"
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#include "type.h"
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#include "icrdma_hw.h"
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static u32 icrdma_regs[IRDMA_MAX_REGS] = {
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PFPE_CQPTAIL,
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PFPE_CQPDB,
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PFPE_CCQPSTATUS,
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PFPE_CCQPHIGH,
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PFPE_CCQPLOW,
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PFPE_CQARM,
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PFPE_CQACK,
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PFPE_AEQALLOC,
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PFPE_CQPERRCODES,
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PFPE_WQEALLOC,
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GLINT_DYN_CTL(0),
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ICRDMA_DB_ADDR_OFFSET,
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GLPCI_LBARCTRL,
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GLPE_CPUSTATUS0,
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GLPE_CPUSTATUS1,
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GLPE_CPUSTATUS2,
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PFINT_AEQCTL,
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GLINT_CEQCTL(0),
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VSIQF_PE_CTL1(0),
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PFHMC_PDINV,
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GLHMC_VFPDINV(0),
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GLPE_CRITERR,
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GLINT_RATE(0),
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};
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static u64 icrdma_masks[IRDMA_MAX_MASKS] = {
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ICRDMA_CCQPSTATUS_CCQP_DONE,
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ICRDMA_CCQPSTATUS_CCQP_ERR,
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ICRDMA_CQPSQ_STAG_PDID,
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ICRDMA_CQPSQ_CQ_CEQID,
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ICRDMA_CQPSQ_CQ_CQID,
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ICRDMA_COMMIT_FPM_CQCNT,
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};
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static u64 icrdma_shifts[IRDMA_MAX_SHIFTS] = {
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ICRDMA_CCQPSTATUS_CCQP_DONE_S,
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ICRDMA_CCQPSTATUS_CCQP_ERR_S,
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ICRDMA_CQPSQ_STAG_PDID_S,
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ICRDMA_CQPSQ_CQ_CEQID_S,
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ICRDMA_CQPSQ_CQ_CQID_S,
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ICRDMA_COMMIT_FPM_CQCNT_S,
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};
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/**
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* icrdma_ena_irq - Enable interrupt
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* @dev: pointer to the device structure
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* @idx: vector index
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*/
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static void icrdma_ena_irq(struct irdma_sc_dev *dev, u32 idx)
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{
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u32 val;
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u32 interval = 0;
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if (dev->ceq_itr && dev->aeq->msix_idx != idx)
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interval = dev->ceq_itr >> 1; /* 2 usec units */
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val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, 0) |
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FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTERVAL, interval) |
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FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 1) |
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FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 1);
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if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
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writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
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else
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writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
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}
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/**
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* icrdma_disable_irq - Disable interrupt
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* @dev: pointer to the device structure
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* @idx: vector index
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*/
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static void icrdma_disable_irq(struct irdma_sc_dev *dev, u32 idx)
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{
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if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
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writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
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else
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writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
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}
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/**
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* icrdma_cfg_ceq- Configure CEQ interrupt
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* @dev: pointer to the device structure
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* @ceq_id: Completion Event Queue ID
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* @idx: vector index
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* @enable: True to enable, False disables
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*/
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static void icrdma_cfg_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
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bool enable)
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{
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u32 reg_val;
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reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |
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FIELD_PREP(IRDMA_GLINT_CEQCTL_MSIX_INDX, idx) |
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FIELD_PREP(IRDMA_GLINT_CEQCTL_ITR_INDX, 3);
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writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
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}
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static const struct irdma_irq_ops icrdma_irq_ops = {
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.irdma_cfg_aeq = irdma_cfg_aeq,
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.irdma_cfg_ceq = icrdma_cfg_ceq,
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.irdma_dis_irq = icrdma_disable_irq,
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.irdma_en_irq = icrdma_ena_irq,
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};
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void icrdma_init_hw(struct irdma_sc_dev *dev)
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{
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int i;
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u8 __iomem *hw_addr;
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for (i = 0; i < IRDMA_MAX_REGS; ++i) {
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hw_addr = dev->hw->hw_addr;
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if (i == IRDMA_DB_ADDR_OFFSET)
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hw_addr = NULL;
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dev->hw_regs[i] = (u32 __iomem *)(hw_addr + icrdma_regs[i]);
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}
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dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID;
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dev->hw_attrs.first_hw_vf_fpm_id = IRDMA_FIRST_VF_FPM_ID;
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for (i = 0; i < IRDMA_MAX_SHIFTS; ++i)
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dev->hw_shifts[i] = icrdma_shifts[i];
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for (i = 0; i < IRDMA_MAX_MASKS; ++i)
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dev->hw_masks[i] = icrdma_masks[i];
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dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
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dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
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dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
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dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
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dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
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dev->irq_ops = &icrdma_irq_ops;
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dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G;
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dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE;
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dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE;
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dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT;
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dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;
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dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE |
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IRDMA_FEATURE_CQ_RESIZE;
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}
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