607 lines
16 KiB
C
607 lines
16 KiB
C
/*
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* Copyright (c) 2010 - 2017 Intel Corporation. All rights reserved.
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* Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/vmalloc.h>
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#include <linux/aer.h>
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#include <linux/module.h>
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#include "qib.h"
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/*
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* This file contains PCIe utility routines that are common to the
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* various QLogic InfiniPath adapters
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*/
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/*
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* Code to adjust PCIe capabilities.
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* To minimize the change footprint, we call it
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* from qib_pcie_params, which every chip-specific
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* file calls, even though this violates some
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* expectations of harmlessness.
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*/
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static void qib_tune_pcie_caps(struct qib_devdata *);
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static void qib_tune_pcie_coalesce(struct qib_devdata *);
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/*
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* Do all the common PCIe setup and initialization.
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* devdata is not yet allocated, and is not allocated until after this
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* routine returns success. Therefore qib_dev_err() can't be used for error
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* printing.
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*/
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int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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int ret;
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ret = pci_enable_device(pdev);
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if (ret) {
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/*
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* This can happen (in theory) iff:
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* We did a chip reset, and then failed to reprogram the
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* BAR, or the chip reset due to an internal error. We then
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* unloaded the driver and reloaded it.
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*
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* Both reset cases set the BAR back to initial state. For
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* the latter case, the AER sticky error bit at offset 0x718
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* should be set, but the Linux kernel doesn't yet know
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* about that, it appears. If the original BAR was retained
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* in the kernel data structures, this may be OK.
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*/
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qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
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-ret);
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goto done;
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}
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ret = pci_request_regions(pdev, QIB_DRV_NAME);
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if (ret) {
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qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
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goto bail;
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}
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ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
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if (ret) {
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/*
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* If the 64 bit setup fails, try 32 bit. Some systems
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* do not setup 64 bit maps on systems with 2GB or less
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* memory installed.
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*/
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ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
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if (ret) {
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qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
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goto bail;
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}
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}
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pci_set_master(pdev);
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ret = pci_enable_pcie_error_reporting(pdev);
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if (ret) {
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qib_early_err(&pdev->dev,
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"Unable to enable pcie error reporting: %d\n",
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ret);
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ret = 0;
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}
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goto done;
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bail:
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pci_disable_device(pdev);
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pci_release_regions(pdev);
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done:
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return ret;
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}
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/*
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* Do remaining PCIe setup, once dd is allocated, and save away
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* fields required to re-initialize after a chip reset, or for
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* various other purposes
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*/
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int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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unsigned long len;
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resource_size_t addr;
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dd->pcidev = pdev;
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pci_set_drvdata(pdev, dd);
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addr = pci_resource_start(pdev, 0);
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len = pci_resource_len(pdev, 0);
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dd->kregbase = ioremap(addr, len);
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if (!dd->kregbase)
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return -ENOMEM;
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dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
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dd->physaddr = addr; /* used for io_remap, etc. */
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/*
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* Save BARs to rewrite after device reset. Save all 64 bits of
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* BAR, just in case.
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*/
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dd->pcibar0 = addr;
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dd->pcibar1 = addr >> 32;
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dd->deviceid = ent->device; /* save for later use */
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dd->vendorid = ent->vendor;
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return 0;
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}
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/*
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* Do PCIe cleanup, after chip-specific cleanup, etc. Just prior
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* to releasing the dd memory.
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* void because none of the core pcie cleanup returns are void
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*/
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void qib_pcie_ddcleanup(struct qib_devdata *dd)
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{
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u64 __iomem *base = (void __iomem *) dd->kregbase;
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dd->kregbase = NULL;
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iounmap(base);
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if (dd->piobase)
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iounmap(dd->piobase);
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if (dd->userbase)
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iounmap(dd->userbase);
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if (dd->piovl15base)
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iounmap(dd->piovl15base);
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pci_disable_device(dd->pcidev);
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pci_release_regions(dd->pcidev);
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pci_set_drvdata(dd->pcidev, NULL);
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}
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/*
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* We save the msi lo and hi values, so we can restore them after
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* chip reset (the kernel PCI infrastructure doesn't yet handle that
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* correctly.
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*/
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static void qib_cache_msi_info(struct qib_devdata *dd, int pos)
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{
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struct pci_dev *pdev = dd->pcidev;
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u16 control;
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pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &dd->msi_lo);
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pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, &dd->msi_hi);
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pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
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/* now save the data (vector) info */
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pci_read_config_word(pdev,
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pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
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&dd->msi_data);
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}
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int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent)
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{
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u16 linkstat, speed;
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int nvec;
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int maxvec;
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unsigned int flags = PCI_IRQ_MSIX | PCI_IRQ_MSI;
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if (!pci_is_pcie(dd->pcidev)) {
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qib_dev_err(dd, "Can't find PCI Express capability!\n");
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/* set up something... */
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dd->lbus_width = 1;
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dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
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nvec = -1;
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goto bail;
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}
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if (dd->flags & QIB_HAS_INTX)
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flags |= PCI_IRQ_LEGACY;
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maxvec = (nent && *nent) ? *nent : 1;
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nvec = pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags);
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if (nvec < 0)
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goto bail;
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/*
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* If nent exists, make sure to record how many vectors were allocated.
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* If msix_enabled is false, return 0 so the fallback code works
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* correctly.
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*/
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if (nent)
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*nent = !dd->pcidev->msix_enabled ? 0 : nvec;
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if (dd->pcidev->msi_enabled)
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qib_cache_msi_info(dd, dd->pcidev->msi_cap);
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pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
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/*
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* speed is bits 0-3, linkwidth is bits 4-8
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* no defines for them in headers
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*/
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speed = linkstat & 0xf;
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linkstat >>= 4;
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linkstat &= 0x1f;
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dd->lbus_width = linkstat;
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switch (speed) {
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case 1:
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dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
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break;
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case 2:
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dd->lbus_speed = 5000; /* Gen1, 5GHz */
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break;
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default: /* not defined, assume gen1 */
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dd->lbus_speed = 2500;
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break;
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}
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/*
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* Check against expected pcie width and complain if "wrong"
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* on first initialization, not afterwards (i.e., reset).
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*/
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if (minw && linkstat < minw)
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qib_dev_err(dd,
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"PCIe width %u (x%u HCA), performance reduced\n",
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linkstat, minw);
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qib_tune_pcie_caps(dd);
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qib_tune_pcie_coalesce(dd);
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bail:
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/* fill in string, even on errors */
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snprintf(dd->lbus_info, sizeof(dd->lbus_info),
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"PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
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return nvec < 0 ? nvec : 0;
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}
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/**
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* qib_free_irq - Cleanup INTx and MSI interrupts
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* @dd: valid pointer to qib dev data
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*
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* Since cleanup for INTx and MSI interrupts is trivial, have a common
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* routine.
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*
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*/
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void qib_free_irq(struct qib_devdata *dd)
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{
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pci_free_irq(dd->pcidev, 0, dd);
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pci_free_irq_vectors(dd->pcidev);
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}
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/*
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* Setup pcie interrupt stuff again after a reset. I'd like to just call
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* pci_enable_msi() again for msi, but when I do that,
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* the MSI enable bit doesn't get set in the command word, and
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* we switch to a different interrupt vector, which is confusing,
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* so I instead just do it all inline. Perhaps somehow can tie this
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* into the PCIe hotplug support at some point
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*/
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int qib_reinit_intr(struct qib_devdata *dd)
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{
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int pos;
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u16 control;
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int ret = 0;
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/* If we aren't using MSI, don't restore it */
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if (!dd->msi_lo)
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goto bail;
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pos = dd->pcidev->msi_cap;
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if (!pos) {
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qib_dev_err(dd,
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"Can't find MSI capability, can't restore MSI settings\n");
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ret = 0;
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/* nothing special for MSIx, just MSI */
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goto bail;
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}
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pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
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dd->msi_lo);
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pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
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dd->msi_hi);
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pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
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if (!(control & PCI_MSI_FLAGS_ENABLE)) {
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control |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
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control);
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}
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/* now rewrite the data (vector) info */
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pci_write_config_word(dd->pcidev, pos +
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((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
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dd->msi_data);
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ret = 1;
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bail:
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qib_free_irq(dd);
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if (!ret && (dd->flags & QIB_HAS_INTX))
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ret = 1;
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/* and now set the pci master bit again */
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pci_set_master(dd->pcidev);
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return ret;
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}
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/*
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* These two routines are helper routines for the device reset code
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* to move all the pcie code out of the chip-specific driver code.
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*/
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void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
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{
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pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
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pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
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pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
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}
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void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
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{
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int r;
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r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
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dd->pcibar0);
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if (r)
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qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
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r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
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dd->pcibar1);
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if (r)
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qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
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/* now re-enable memory access, and restore cosmetic settings */
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pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
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pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
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pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
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r = pci_enable_device(dd->pcidev);
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if (r)
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qib_dev_err(dd,
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"pci_enable_device failed after reset: %d\n", r);
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}
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static int qib_pcie_coalesce;
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module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
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MODULE_PARM_DESC(pcie_coalesce, "tune PCIe coalescing on some Intel chipsets");
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/*
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* Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
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* chipsets. This is known to be unsafe for some revisions of some
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* of these chipsets, with some BIOS settings, and enabling it on those
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* systems may result in the system crashing, and/or data corruption.
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*/
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static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
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{
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struct pci_dev *parent;
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u16 devid;
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u32 mask, bits, val;
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if (!qib_pcie_coalesce)
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return;
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/* Find out supported and configured values for parent (root) */
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parent = dd->pcidev->bus->self;
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if (parent->bus->parent) {
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qib_devinfo(dd->pcidev, "Parent not root\n");
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return;
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}
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if (!pci_is_pcie(parent))
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return;
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if (parent->vendor != 0x8086)
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return;
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/*
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* - bit 12: Max_rdcmp_Imt_EN: need to set to 1
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* - bit 11: COALESCE_FORCE: need to set to 0
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* - bit 10: COALESCE_EN: need to set to 1
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* (but limitations on some on some chipsets)
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*
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* On the Intel 5000, 5100, and 7300 chipsets, there is
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* also: - bit 25:24: COALESCE_MODE, need to set to 0
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*/
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devid = parent->device;
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if (devid >= 0x25e2 && devid <= 0x25fa) {
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/* 5000 P/V/X/Z */
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if (parent->revision <= 0xb2)
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bits = 1U << 10;
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else
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bits = 7U << 10;
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mask = (3U << 24) | (7U << 10);
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} else if (devid >= 0x65e2 && devid <= 0x65fa) {
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/* 5100 */
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bits = 1U << 10;
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mask = (3U << 24) | (7U << 10);
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} else if (devid >= 0x4021 && devid <= 0x402e) {
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/* 5400 */
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bits = 7U << 10;
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mask = 7U << 10;
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} else if (devid >= 0x3604 && devid <= 0x360a) {
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/* 7300 */
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bits = 7U << 10;
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mask = (3U << 24) | (7U << 10);
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} else {
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/* not one of the chipsets that we know about */
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return;
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}
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pci_read_config_dword(parent, 0x48, &val);
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val &= ~mask;
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val |= bits;
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pci_write_config_dword(parent, 0x48, val);
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}
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/*
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* BIOS may not set PCIe bus-utilization parameters for best performance.
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* Check and optionally adjust them to maximize our throughput.
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*/
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static int qib_pcie_caps;
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module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
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MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
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static void qib_tune_pcie_caps(struct qib_devdata *dd)
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{
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struct pci_dev *parent;
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u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
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u16 rc_mrrs, ep_mrrs, max_mrrs;
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/* Find out supported and configured values for parent (root) */
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parent = dd->pcidev->bus->self;
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if (!pci_is_root_bus(parent->bus)) {
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qib_devinfo(dd->pcidev, "Parent not root\n");
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return;
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}
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if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
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return;
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rc_mpss = parent->pcie_mpss;
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rc_mps = ffs(pcie_get_mps(parent)) - 8;
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/* Find out supported and configured values for endpoint (us) */
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ep_mpss = dd->pcidev->pcie_mpss;
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ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
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/* Find max payload supported by root, endpoint */
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if (rc_mpss > ep_mpss)
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rc_mpss = ep_mpss;
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/* If Supported greater than limit in module param, limit it */
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if (rc_mpss > (qib_pcie_caps & 7))
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rc_mpss = qib_pcie_caps & 7;
|
|
/* If less than (allowed, supported), bump root payload */
|
|
if (rc_mpss > rc_mps) {
|
|
rc_mps = rc_mpss;
|
|
pcie_set_mps(parent, 128 << rc_mps);
|
|
}
|
|
/* If less than (allowed, supported), bump endpoint payload */
|
|
if (rc_mpss > ep_mps) {
|
|
ep_mps = rc_mpss;
|
|
pcie_set_mps(dd->pcidev, 128 << ep_mps);
|
|
}
|
|
|
|
/*
|
|
* Now the Read Request size.
|
|
* No field for max supported, but PCIe spec limits it to 4096,
|
|
* which is code '5' (log2(4096) - 7)
|
|
*/
|
|
max_mrrs = 5;
|
|
if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
|
|
max_mrrs = (qib_pcie_caps >> 4) & 7;
|
|
|
|
max_mrrs = 128 << max_mrrs;
|
|
rc_mrrs = pcie_get_readrq(parent);
|
|
ep_mrrs = pcie_get_readrq(dd->pcidev);
|
|
|
|
if (max_mrrs > rc_mrrs) {
|
|
rc_mrrs = max_mrrs;
|
|
pcie_set_readrq(parent, rc_mrrs);
|
|
}
|
|
if (max_mrrs > ep_mrrs) {
|
|
ep_mrrs = max_mrrs;
|
|
pcie_set_readrq(dd->pcidev, ep_mrrs);
|
|
}
|
|
}
|
|
/* End of PCIe capability tuning */
|
|
|
|
/*
|
|
* From here through qib_pci_err_handler definition is invoked via
|
|
* PCI error infrastructure, registered via pci
|
|
*/
|
|
static pci_ers_result_t
|
|
qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
|
|
{
|
|
struct qib_devdata *dd = pci_get_drvdata(pdev);
|
|
pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
|
|
|
|
switch (state) {
|
|
case pci_channel_io_normal:
|
|
qib_devinfo(pdev, "State Normal, ignoring\n");
|
|
break;
|
|
|
|
case pci_channel_io_frozen:
|
|
qib_devinfo(pdev, "State Frozen, requesting reset\n");
|
|
pci_disable_device(pdev);
|
|
ret = PCI_ERS_RESULT_NEED_RESET;
|
|
break;
|
|
|
|
case pci_channel_io_perm_failure:
|
|
qib_devinfo(pdev, "State Permanent Failure, disabling\n");
|
|
if (dd) {
|
|
/* no more register accesses! */
|
|
dd->flags &= ~QIB_PRESENT;
|
|
qib_disable_after_error(dd);
|
|
}
|
|
/* else early, or other problem */
|
|
ret = PCI_ERS_RESULT_DISCONNECT;
|
|
break;
|
|
|
|
default: /* shouldn't happen */
|
|
qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
|
|
state);
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static pci_ers_result_t
|
|
qib_pci_mmio_enabled(struct pci_dev *pdev)
|
|
{
|
|
u64 words = 0U;
|
|
struct qib_devdata *dd = pci_get_drvdata(pdev);
|
|
pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
|
|
|
|
if (dd && dd->pport) {
|
|
words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
|
|
if (words == ~0ULL)
|
|
ret = PCI_ERS_RESULT_NEED_RESET;
|
|
}
|
|
qib_devinfo(pdev,
|
|
"QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
|
|
words, ret);
|
|
return ret;
|
|
}
|
|
|
|
static pci_ers_result_t
|
|
qib_pci_slot_reset(struct pci_dev *pdev)
|
|
{
|
|
qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
|
|
return PCI_ERS_RESULT_CAN_RECOVER;
|
|
}
|
|
|
|
static void
|
|
qib_pci_resume(struct pci_dev *pdev)
|
|
{
|
|
struct qib_devdata *dd = pci_get_drvdata(pdev);
|
|
|
|
qib_devinfo(pdev, "QIB resume function called\n");
|
|
/*
|
|
* Running jobs will fail, since it's asynchronous
|
|
* unlike sysfs-requested reset. Better than
|
|
* doing nothing.
|
|
*/
|
|
qib_init(dd, 1); /* same as re-init after reset */
|
|
}
|
|
|
|
const struct pci_error_handlers qib_pci_err_handler = {
|
|
.error_detected = qib_pci_error_detected,
|
|
.mmio_enabled = qib_pci_mmio_enabled,
|
|
.slot_reset = qib_pci_slot_reset,
|
|
.resume = qib_pci_resume,
|
|
};
|