260 lines
7.1 KiB
C
260 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* DFL device driver for EMIF private feature
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*
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* Copyright (C) 2020 Intel Corporation, Inc.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/dfl.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define FME_FEATURE_ID_EMIF 0x9
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#define EMIF_STAT 0x8
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#define EMIF_STAT_INIT_DONE_SFT 0
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#define EMIF_STAT_CALC_FAIL_SFT 8
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#define EMIF_STAT_CLEAR_BUSY_SFT 16
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#define EMIF_CTRL 0x10
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#define EMIF_CTRL_CLEAR_EN_SFT 0
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#define EMIF_CTRL_CLEAR_EN_MSK GENMASK_ULL(7, 0)
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#define EMIF_POLL_INVL 10000 /* us */
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#define EMIF_POLL_TIMEOUT 5000000 /* us */
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/*
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* The Capability Register replaces the Control Register (at the same
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* offset) for EMIF feature revisions > 0. The bitmask that indicates
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* the presence of memory channels exists in both the Capability Register
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* and Control Register definitions. These can be thought of as a C union.
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* The Capability Register definitions are used to check for the existence
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* of a memory channel, and the Control Register definitions are used for
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* managing the memory-clear functionality in revision 0.
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*/
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#define EMIF_CAPABILITY_BASE 0x10
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#define EMIF_CAPABILITY_CHN_MSK_V0 GENMASK_ULL(3, 0)
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#define EMIF_CAPABILITY_CHN_MSK GENMASK_ULL(7, 0)
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struct dfl_emif {
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struct device *dev;
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void __iomem *base;
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spinlock_t lock; /* Serialises access to EMIF_CTRL reg */
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};
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struct emif_attr {
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struct device_attribute attr;
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u32 shift;
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u32 index;
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};
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#define to_emif_attr(dev_attr) \
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container_of(dev_attr, struct emif_attr, attr)
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static ssize_t emif_state_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct emif_attr *eattr = to_emif_attr(attr);
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struct dfl_emif *de = dev_get_drvdata(dev);
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u64 val;
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val = readq(de->base + EMIF_STAT);
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return sysfs_emit(buf, "%u\n",
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!!(val & BIT_ULL(eattr->shift + eattr->index)));
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}
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static ssize_t emif_clear_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct emif_attr *eattr = to_emif_attr(attr);
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struct dfl_emif *de = dev_get_drvdata(dev);
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u64 clear_busy_msk, clear_en_msk, val;
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void __iomem *base = de->base;
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if (!sysfs_streq(buf, "1"))
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return -EINVAL;
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clear_busy_msk = BIT_ULL(EMIF_STAT_CLEAR_BUSY_SFT + eattr->index);
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clear_en_msk = BIT_ULL(EMIF_CTRL_CLEAR_EN_SFT + eattr->index);
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spin_lock(&de->lock);
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/* The CLEAR_EN field is WO, but other fields are RW */
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val = readq(base + EMIF_CTRL);
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val &= ~EMIF_CTRL_CLEAR_EN_MSK;
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val |= clear_en_msk;
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writeq(val, base + EMIF_CTRL);
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spin_unlock(&de->lock);
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if (readq_poll_timeout(base + EMIF_STAT, val,
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!(val & clear_busy_msk),
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EMIF_POLL_INVL, EMIF_POLL_TIMEOUT)) {
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dev_err(de->dev, "timeout, fail to clear\n");
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return -ETIMEDOUT;
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}
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return count;
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}
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#define emif_state_attr(_name, _shift, _index) \
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static struct emif_attr emif_attr_##inf##_index##_##_name = \
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{ .attr = __ATTR(inf##_index##_##_name, 0444, \
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emif_state_show, NULL), \
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.shift = (_shift), .index = (_index) }
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#define emif_clear_attr(_index) \
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static struct emif_attr emif_attr_##inf##_index##_clear = \
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{ .attr = __ATTR(inf##_index##_clear, 0200, \
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NULL, emif_clear_store), \
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.index = (_index) }
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 0);
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 1);
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 2);
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 3);
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 4);
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 5);
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 6);
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emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 7);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 0);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 1);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 2);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 3);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 4);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 5);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 6);
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emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 7);
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emif_clear_attr(0);
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emif_clear_attr(1);
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emif_clear_attr(2);
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emif_clear_attr(3);
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emif_clear_attr(4);
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emif_clear_attr(5);
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emif_clear_attr(6);
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emif_clear_attr(7);
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static struct attribute *dfl_emif_attrs[] = {
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&emif_attr_inf0_init_done.attr.attr,
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&emif_attr_inf0_cal_fail.attr.attr,
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&emif_attr_inf0_clear.attr.attr,
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&emif_attr_inf1_init_done.attr.attr,
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&emif_attr_inf1_cal_fail.attr.attr,
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&emif_attr_inf1_clear.attr.attr,
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&emif_attr_inf2_init_done.attr.attr,
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&emif_attr_inf2_cal_fail.attr.attr,
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&emif_attr_inf2_clear.attr.attr,
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&emif_attr_inf3_init_done.attr.attr,
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&emif_attr_inf3_cal_fail.attr.attr,
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&emif_attr_inf3_clear.attr.attr,
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&emif_attr_inf4_init_done.attr.attr,
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&emif_attr_inf4_cal_fail.attr.attr,
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&emif_attr_inf4_clear.attr.attr,
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&emif_attr_inf5_init_done.attr.attr,
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&emif_attr_inf5_cal_fail.attr.attr,
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&emif_attr_inf5_clear.attr.attr,
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&emif_attr_inf6_init_done.attr.attr,
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&emif_attr_inf6_cal_fail.attr.attr,
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&emif_attr_inf6_clear.attr.attr,
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&emif_attr_inf7_init_done.attr.attr,
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&emif_attr_inf7_cal_fail.attr.attr,
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&emif_attr_inf7_clear.attr.attr,
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NULL,
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};
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static umode_t dfl_emif_visible(struct kobject *kobj,
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struct attribute *attr, int n)
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{
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struct dfl_emif *de = dev_get_drvdata(kobj_to_dev(kobj));
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struct emif_attr *eattr = container_of(attr, struct emif_attr,
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attr.attr);
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struct dfl_device *ddev = to_dfl_dev(de->dev);
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u64 val;
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/*
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* This device supports up to 8 memory interfaces, but not all
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* interfaces are used on different platforms. The read out value of
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* CAPABILITY_CHN_MSK field (which is a bitmap) indicates which
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* interfaces are available.
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*/
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if (ddev->revision > 0 && strstr(attr->name, "_clear"))
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return 0;
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if (ddev->revision == 0)
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val = FIELD_GET(EMIF_CAPABILITY_CHN_MSK_V0,
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readq(de->base + EMIF_CAPABILITY_BASE));
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else
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val = FIELD_GET(EMIF_CAPABILITY_CHN_MSK,
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readq(de->base + EMIF_CAPABILITY_BASE));
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return (val & BIT_ULL(eattr->index)) ? attr->mode : 0;
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}
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static const struct attribute_group dfl_emif_group = {
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.is_visible = dfl_emif_visible,
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.attrs = dfl_emif_attrs,
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};
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static const struct attribute_group *dfl_emif_groups[] = {
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&dfl_emif_group,
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NULL,
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};
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static int dfl_emif_probe(struct dfl_device *ddev)
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{
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struct device *dev = &ddev->dev;
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struct dfl_emif *de;
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de = devm_kzalloc(dev, sizeof(*de), GFP_KERNEL);
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if (!de)
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return -ENOMEM;
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de->base = devm_ioremap_resource(dev, &ddev->mmio_res);
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if (IS_ERR(de->base))
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return PTR_ERR(de->base);
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de->dev = dev;
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spin_lock_init(&de->lock);
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dev_set_drvdata(dev, de);
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return 0;
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}
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static const struct dfl_device_id dfl_emif_ids[] = {
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{ FME_ID, FME_FEATURE_ID_EMIF },
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{ }
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};
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MODULE_DEVICE_TABLE(dfl, dfl_emif_ids);
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static struct dfl_driver dfl_emif_driver = {
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.drv = {
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.name = "dfl-emif",
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.dev_groups = dfl_emif_groups,
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},
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.id_table = dfl_emif_ids,
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.probe = dfl_emif_probe,
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};
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module_dfl_driver(dfl_emif_driver);
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MODULE_DESCRIPTION("DFL EMIF driver");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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