482 lines
12 KiB
C
482 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* A driver for the Integrated Circuits ICS932S401
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* Copyright (C) 2008 IBM
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*
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* Author: Darrick J. Wong <darrick.wong@oracle.com>
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*/
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#include <linux/module.h>
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#include <linux/jiffies.h>
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#include <linux/i2c.h>
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#include <linux/err.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/log2.h>
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#include <linux/slab.h>
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/* Addresses to scan */
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static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END };
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/* ICS932S401 registers */
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#define ICS932S401_REG_CFG2 0x01
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#define ICS932S401_CFG1_SPREAD 0x01
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#define ICS932S401_REG_CFG7 0x06
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#define ICS932S401_FS_MASK 0x07
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#define ICS932S401_REG_VENDOR_REV 0x07
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#define ICS932S401_VENDOR 1
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#define ICS932S401_VENDOR_MASK 0x0F
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#define ICS932S401_REV 4
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#define ICS932S401_REV_SHIFT 4
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#define ICS932S401_REG_DEVICE 0x09
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#define ICS932S401_DEVICE 11
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#define ICS932S401_REG_CTRL 0x0A
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#define ICS932S401_MN_ENABLED 0x80
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#define ICS932S401_CPU_ALT 0x04
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#define ICS932S401_SRC_ALT 0x08
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#define ICS932S401_REG_CPU_M_CTRL 0x0B
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#define ICS932S401_M_MASK 0x3F
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#define ICS932S401_REG_CPU_N_CTRL 0x0C
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#define ICS932S401_REG_CPU_SPREAD1 0x0D
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#define ICS932S401_REG_CPU_SPREAD2 0x0E
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#define ICS932S401_SPREAD_MASK 0x7FFF
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#define ICS932S401_REG_SRC_M_CTRL 0x0F
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#define ICS932S401_REG_SRC_N_CTRL 0x10
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#define ICS932S401_REG_SRC_SPREAD1 0x11
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#define ICS932S401_REG_SRC_SPREAD2 0x12
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#define ICS932S401_REG_CPU_DIVISOR 0x13
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#define ICS932S401_CPU_DIVISOR_SHIFT 4
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#define ICS932S401_REG_PCISRC_DIVISOR 0x14
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#define ICS932S401_SRC_DIVISOR_MASK 0x0F
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#define ICS932S401_PCI_DIVISOR_SHIFT 4
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/* Base clock is 14.318MHz */
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#define BASE_CLOCK 14318
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#define NUM_REGS 21
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#define NUM_MIRRORED_REGS 15
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static int regs_to_copy[NUM_MIRRORED_REGS] = {
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ICS932S401_REG_CFG2,
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ICS932S401_REG_CFG7,
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ICS932S401_REG_VENDOR_REV,
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ICS932S401_REG_DEVICE,
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ICS932S401_REG_CTRL,
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ICS932S401_REG_CPU_M_CTRL,
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ICS932S401_REG_CPU_N_CTRL,
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ICS932S401_REG_CPU_SPREAD1,
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ICS932S401_REG_CPU_SPREAD2,
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ICS932S401_REG_SRC_M_CTRL,
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ICS932S401_REG_SRC_N_CTRL,
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ICS932S401_REG_SRC_SPREAD1,
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ICS932S401_REG_SRC_SPREAD2,
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ICS932S401_REG_CPU_DIVISOR,
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ICS932S401_REG_PCISRC_DIVISOR,
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};
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/* How often do we reread sensors values? (In jiffies) */
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#define SENSOR_REFRESH_INTERVAL (2 * HZ)
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/* How often do we reread sensor limit values? (In jiffies) */
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#define LIMIT_REFRESH_INTERVAL (60 * HZ)
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struct ics932s401_data {
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struct attribute_group attrs;
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struct mutex lock;
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char sensors_valid;
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unsigned long sensors_last_updated; /* In jiffies */
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u8 regs[NUM_REGS];
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};
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static int ics932s401_probe(struct i2c_client *client);
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static int ics932s401_detect(struct i2c_client *client,
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struct i2c_board_info *info);
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static void ics932s401_remove(struct i2c_client *client);
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static const struct i2c_device_id ics932s401_id[] = {
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{ "ics932s401", 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, ics932s401_id);
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static struct i2c_driver ics932s401_driver = {
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.class = I2C_CLASS_HWMON,
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.driver = {
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.name = "ics932s401",
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},
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.probe_new = ics932s401_probe,
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.remove = ics932s401_remove,
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.id_table = ics932s401_id,
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.detect = ics932s401_detect,
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.address_list = normal_i2c,
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};
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static struct ics932s401_data *ics932s401_update_device(struct device *dev)
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{
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struct i2c_client *client = to_i2c_client(dev);
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struct ics932s401_data *data = i2c_get_clientdata(client);
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unsigned long local_jiffies = jiffies;
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int i, temp;
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mutex_lock(&data->lock);
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if (time_before(local_jiffies, data->sensors_last_updated +
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SENSOR_REFRESH_INTERVAL)
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&& data->sensors_valid)
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goto out;
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/*
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* Each register must be read as a word and then right shifted 8 bits.
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* Not really sure why this is; setting the "byte count programming"
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* register to 1 does not fix this problem.
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*/
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for (i = 0; i < NUM_MIRRORED_REGS; i++) {
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temp = i2c_smbus_read_word_data(client, regs_to_copy[i]);
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if (temp < 0)
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temp = 0;
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data->regs[regs_to_copy[i]] = temp >> 8;
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}
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data->sensors_last_updated = local_jiffies;
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data->sensors_valid = 1;
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out:
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mutex_unlock(&data->lock);
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return data;
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}
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static ssize_t show_spread_enabled(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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if (data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD)
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return sprintf(buf, "1\n");
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return sprintf(buf, "0\n");
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}
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/* bit to cpu khz map */
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static const int fs_speeds[] = {
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266666,
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133333,
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200000,
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166666,
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333333,
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100000,
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400000,
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0,
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};
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/* clock divisor map */
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static const int divisors[] = {2, 3, 5, 15, 4, 6, 10, 30, 8, 12, 20, 60, 16,
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24, 40, 120};
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/* Calculate CPU frequency from the M/N registers. */
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static int calculate_cpu_freq(struct ics932s401_data *data)
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{
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int m, n, freq;
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m = data->regs[ICS932S401_REG_CPU_M_CTRL] & ICS932S401_M_MASK;
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n = data->regs[ICS932S401_REG_CPU_N_CTRL];
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/* Pull in bits 8 & 9 from the M register */
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n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x80) << 1;
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n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x40) << 3;
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freq = BASE_CLOCK * (n + 8) / (m + 2);
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freq /= divisors[data->regs[ICS932S401_REG_CPU_DIVISOR] >>
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ICS932S401_CPU_DIVISOR_SHIFT];
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return freq;
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}
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static ssize_t show_cpu_clock(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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return sprintf(buf, "%d\n", calculate_cpu_freq(data));
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}
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static ssize_t show_cpu_clock_sel(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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int freq;
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if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
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freq = calculate_cpu_freq(data);
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else {
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/* Freq is neatly wrapped up for us */
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int fid = data->regs[ICS932S401_REG_CFG7] & ICS932S401_FS_MASK;
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freq = fs_speeds[fid];
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if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT) {
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switch (freq) {
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case 166666:
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freq = 160000;
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break;
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case 333333:
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freq = 320000;
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break;
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}
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}
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}
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return sprintf(buf, "%d\n", freq);
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}
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/* Calculate SRC frequency from the M/N registers. */
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static int calculate_src_freq(struct ics932s401_data *data)
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{
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int m, n, freq;
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m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
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n = data->regs[ICS932S401_REG_SRC_N_CTRL];
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/* Pull in bits 8 & 9 from the M register */
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n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
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n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
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freq = BASE_CLOCK * (n + 8) / (m + 2);
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freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] &
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ICS932S401_SRC_DIVISOR_MASK];
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return freq;
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}
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static ssize_t show_src_clock(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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return sprintf(buf, "%d\n", calculate_src_freq(data));
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}
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static ssize_t show_src_clock_sel(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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int freq;
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if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
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freq = calculate_src_freq(data);
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else
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/* Freq is neatly wrapped up for us */
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if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT &&
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data->regs[ICS932S401_REG_CTRL] & ICS932S401_SRC_ALT)
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freq = 96000;
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else
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freq = 100000;
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return sprintf(buf, "%d\n", freq);
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}
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/* Calculate PCI frequency from the SRC M/N registers. */
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static int calculate_pci_freq(struct ics932s401_data *data)
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{
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int m, n, freq;
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m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
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n = data->regs[ICS932S401_REG_SRC_N_CTRL];
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/* Pull in bits 8 & 9 from the M register */
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n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
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n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
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freq = BASE_CLOCK * (n + 8) / (m + 2);
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freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] >>
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ICS932S401_PCI_DIVISOR_SHIFT];
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return freq;
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}
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static ssize_t show_pci_clock(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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return sprintf(buf, "%d\n", calculate_pci_freq(data));
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}
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static ssize_t show_pci_clock_sel(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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int freq;
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if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
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freq = calculate_pci_freq(data);
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else
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freq = 33333;
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return sprintf(buf, "%d\n", freq);
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}
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static ssize_t show_value(struct device *dev,
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struct device_attribute *devattr,
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char *buf);
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static ssize_t show_spread(struct device *dev,
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struct device_attribute *devattr,
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char *buf);
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static DEVICE_ATTR(spread_enabled, S_IRUGO, show_spread_enabled, NULL);
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static DEVICE_ATTR(cpu_clock_selection, S_IRUGO, show_cpu_clock_sel, NULL);
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static DEVICE_ATTR(cpu_clock, S_IRUGO, show_cpu_clock, NULL);
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static DEVICE_ATTR(src_clock_selection, S_IRUGO, show_src_clock_sel, NULL);
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static DEVICE_ATTR(src_clock, S_IRUGO, show_src_clock, NULL);
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static DEVICE_ATTR(pci_clock_selection, S_IRUGO, show_pci_clock_sel, NULL);
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static DEVICE_ATTR(pci_clock, S_IRUGO, show_pci_clock, NULL);
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static DEVICE_ATTR(usb_clock, S_IRUGO, show_value, NULL);
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static DEVICE_ATTR(ref_clock, S_IRUGO, show_value, NULL);
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static DEVICE_ATTR(cpu_spread, S_IRUGO, show_spread, NULL);
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static DEVICE_ATTR(src_spread, S_IRUGO, show_spread, NULL);
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static struct attribute *ics932s401_attr[] = {
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&dev_attr_spread_enabled.attr,
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&dev_attr_cpu_clock_selection.attr,
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&dev_attr_cpu_clock.attr,
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&dev_attr_src_clock_selection.attr,
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&dev_attr_src_clock.attr,
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&dev_attr_pci_clock_selection.attr,
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&dev_attr_pci_clock.attr,
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&dev_attr_usb_clock.attr,
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&dev_attr_ref_clock.attr,
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&dev_attr_cpu_spread.attr,
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&dev_attr_src_spread.attr,
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NULL
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};
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static ssize_t show_value(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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int x;
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if (devattr == &dev_attr_usb_clock)
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x = 48000;
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else if (devattr == &dev_attr_ref_clock)
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x = BASE_CLOCK;
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else
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BUG();
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return sprintf(buf, "%d\n", x);
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}
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static ssize_t show_spread(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct ics932s401_data *data = ics932s401_update_device(dev);
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int reg;
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unsigned long val;
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if (!(data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD))
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return sprintf(buf, "0%%\n");
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if (devattr == &dev_attr_src_spread)
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reg = ICS932S401_REG_SRC_SPREAD1;
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else if (devattr == &dev_attr_cpu_spread)
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reg = ICS932S401_REG_CPU_SPREAD1;
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else
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BUG();
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val = data->regs[reg] | (data->regs[reg + 1] << 8);
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val &= ICS932S401_SPREAD_MASK;
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/* Scale 0..2^14 to -0.5. */
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val = 500000 * val / 16384;
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return sprintf(buf, "-0.%lu%%\n", val);
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}
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/* Return 0 if detection is successful, -ENODEV otherwise */
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static int ics932s401_detect(struct i2c_client *client,
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struct i2c_board_info *info)
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{
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struct i2c_adapter *adapter = client->adapter;
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int vendor, device, revision;
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if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
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return -ENODEV;
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vendor = i2c_smbus_read_word_data(client, ICS932S401_REG_VENDOR_REV);
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vendor >>= 8;
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revision = vendor >> ICS932S401_REV_SHIFT;
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vendor &= ICS932S401_VENDOR_MASK;
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if (vendor != ICS932S401_VENDOR)
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return -ENODEV;
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device = i2c_smbus_read_word_data(client, ICS932S401_REG_DEVICE);
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device >>= 8;
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if (device != ICS932S401_DEVICE)
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return -ENODEV;
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if (revision != ICS932S401_REV)
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dev_info(&adapter->dev, "Unknown revision %d\n", revision);
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strscpy(info->type, "ics932s401", I2C_NAME_SIZE);
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return 0;
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}
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static int ics932s401_probe(struct i2c_client *client)
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{
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struct ics932s401_data *data;
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int err;
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data = kzalloc(sizeof(struct ics932s401_data), GFP_KERNEL);
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if (!data) {
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err = -ENOMEM;
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goto exit;
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}
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i2c_set_clientdata(client, data);
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mutex_init(&data->lock);
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dev_info(&client->dev, "%s chip found\n", client->name);
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/* Register sysfs hooks */
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data->attrs.attrs = ics932s401_attr;
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err = sysfs_create_group(&client->dev.kobj, &data->attrs);
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if (err)
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goto exit_free;
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return 0;
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exit_free:
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kfree(data);
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exit:
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return err;
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}
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static void ics932s401_remove(struct i2c_client *client)
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{
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struct ics932s401_data *data = i2c_get_clientdata(client);
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sysfs_remove_group(&client->dev.kobj, &data->attrs);
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kfree(data);
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}
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module_i2c_driver(ics932s401_driver);
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MODULE_AUTHOR("Darrick J. Wong <darrick.wong@oracle.com>");
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MODULE_DESCRIPTION("ICS932S401 driver");
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MODULE_LICENSE("GPL");
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/* IBM IntelliStation Z30 */
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MODULE_ALIAS("dmi:bvnIBM:*:rn9228:*");
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MODULE_ALIAS("dmi:bvnIBM:*:rn9232:*");
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/* IBM x3650/x3550 */
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MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3650*");
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MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3550*");
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