1117 lines
30 KiB
C
1117 lines
30 KiB
C
/*
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* SMI (Serial Memory Controller) device driver for Serial NOR Flash on
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* SPEAr platform
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* The serial nor interface is largely based on m25p80.c, however the SPI
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* interface has been replaced by SMI.
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*
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* Copyright © 2010 STMicroelectronics.
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* Ashish Priyadarshi
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* Shiraz Hashim <shiraz.linux.kernel@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spear_smi.h>
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#include <linux/mutex.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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/* SMI clock rate */
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#define SMI_MAX_CLOCK_FREQ 50000000 /* 50 MHz */
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/* MAX time out to safely come out of a erase or write busy conditions */
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#define SMI_PROBE_TIMEOUT (HZ / 10)
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#define SMI_MAX_TIME_OUT (3 * HZ)
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/* timeout for command completion */
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#define SMI_CMD_TIMEOUT (HZ / 10)
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/* registers of smi */
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#define SMI_CR1 0x0 /* SMI control register 1 */
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#define SMI_CR2 0x4 /* SMI control register 2 */
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#define SMI_SR 0x8 /* SMI status register */
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#define SMI_TR 0xC /* SMI transmit register */
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#define SMI_RR 0x10 /* SMI receive register */
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/* defines for control_reg 1 */
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#define BANK_EN (0xF << 0) /* enables all banks */
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#define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */
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#define SW_MODE (0x1 << 28) /* enables SW Mode */
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#define WB_MODE (0x1 << 29) /* Write Burst Mode */
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#define FAST_MODE (0x1 << 15) /* Fast Mode */
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#define HOLD1 (0x1 << 16) /* Clock Hold period selection */
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/* defines for control_reg 2 */
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#define SEND (0x1 << 7) /* Send data */
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#define TFIE (0x1 << 8) /* Transmission Flag Interrupt Enable */
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#define WCIE (0x1 << 9) /* Write Complete Interrupt Enable */
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#define RD_STATUS_REG (0x1 << 10) /* reads status reg */
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#define WE (0x1 << 11) /* Write Enable */
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#define TX_LEN_SHIFT 0
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#define RX_LEN_SHIFT 4
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#define BANK_SHIFT 12
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/* defines for status register */
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#define SR_WIP 0x1 /* Write in progress */
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#define SR_WEL 0x2 /* Write enable latch */
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#define SR_BP0 0x4 /* Block protect 0 */
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#define SR_BP1 0x8 /* Block protect 1 */
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#define SR_BP2 0x10 /* Block protect 2 */
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#define SR_SRWD 0x80 /* SR write protect */
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#define TFF 0x100 /* Transfer Finished Flag */
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#define WCF 0x200 /* Transfer Finished Flag */
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#define ERF1 0x400 /* Forbidden Write Request */
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#define ERF2 0x800 /* Forbidden Access */
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#define WM_SHIFT 12
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/* flash opcodes */
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#define OPCODE_RDID 0x9f /* Read JEDEC ID */
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/* Flash Device Ids maintenance section */
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/* data structure to maintain flash ids from different vendors */
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struct flash_device {
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char *name;
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u8 erase_cmd;
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u32 device_id;
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u32 pagesize;
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unsigned long sectorsize;
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unsigned long size_in_bytes;
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};
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#define FLASH_ID(n, es, id, psize, ssize, size) \
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{ \
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.name = n, \
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.erase_cmd = es, \
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.device_id = id, \
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.pagesize = psize, \
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.sectorsize = ssize, \
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.size_in_bytes = size \
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}
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static struct flash_device flash_devices[] = {
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FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
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FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
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FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
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FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
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FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
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FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
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FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
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FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
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FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
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FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
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FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
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FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
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FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
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FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
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FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
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FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
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FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
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FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
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FLASH_ID("atmel 25f512" , 0x52, 0x0065001F, 0x80 , 0x8000 , 0x10000),
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FLASH_ID("atmel 25f1024" , 0x52, 0x0060001F, 0x100, 0x8000 , 0x20000),
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FLASH_ID("atmel 25f2048" , 0x52, 0x0063001F, 0x100, 0x10000, 0x40000),
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FLASH_ID("atmel 25f4096" , 0x52, 0x0064001F, 0x100, 0x10000, 0x80000),
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FLASH_ID("atmel 25fs040" , 0xd7, 0x0004661F, 0x100, 0x10000, 0x80000),
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FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
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FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
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FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
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FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
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FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
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FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
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FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
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FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
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FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
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FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
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FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
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};
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/* Define spear specific structures */
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struct spear_snor_flash;
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/**
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* struct spear_smi - Structure for SMI Device
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*
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* @clk: functional clock
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* @status: current status register of SMI.
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* @clk_rate: functional clock rate of SMI (default: SMI_MAX_CLOCK_FREQ)
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* @lock: lock to prevent parallel access of SMI.
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* @io_base: base address for registers of SMI.
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* @pdev: platform device
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* @cmd_complete: queue to wait for command completion of NOR-flash.
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* @num_flashes: number of flashes actually present on board.
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* @flash: separate structure for each Serial NOR-flash attached to SMI.
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*/
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struct spear_smi {
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struct clk *clk;
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u32 status;
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unsigned long clk_rate;
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struct mutex lock;
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void __iomem *io_base;
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struct platform_device *pdev;
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wait_queue_head_t cmd_complete;
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u32 num_flashes;
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struct spear_snor_flash *flash[MAX_NUM_FLASH_CHIP];
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};
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/**
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* struct spear_snor_flash - Structure for Serial NOR Flash
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*
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* @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
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* @dev_id: Device ID of NOR-flash.
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* @lock: lock to manage flash read, write and erase operations
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* @mtd: MTD info for each NOR-flash.
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* @num_parts: Total number of partition in each bank of NOR-flash.
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* @parts: Partition info for each bank of NOR-flash.
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* @page_size: Page size of NOR-flash.
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* @base_addr: Base address of NOR-flash.
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* @erase_cmd: erase command may vary on different flash types
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* @fast_mode: flash supports read in fast mode
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*/
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struct spear_snor_flash {
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u32 bank;
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u32 dev_id;
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struct mutex lock;
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struct mtd_info mtd;
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u32 num_parts;
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struct mtd_partition *parts;
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u32 page_size;
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void __iomem *base_addr;
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u8 erase_cmd;
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u8 fast_mode;
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};
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static inline struct spear_snor_flash *get_flash_data(struct mtd_info *mtd)
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{
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return container_of(mtd, struct spear_snor_flash, mtd);
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}
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/**
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* spear_smi_read_sr - Read status register of flash through SMI
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* @dev: structure of SMI information.
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* @bank: bank to which flash is connected
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*
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* This routine will return the status register of the flash chip present at the
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* given bank.
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*/
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static int spear_smi_read_sr(struct spear_smi *dev, u32 bank)
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{
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int ret;
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u32 ctrlreg1;
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mutex_lock(&dev->lock);
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dev->status = 0; /* Will be set in interrupt handler */
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ctrlreg1 = readl(dev->io_base + SMI_CR1);
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/* program smi in hw mode */
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writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);
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/* performing a rsr instruction in hw mode */
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writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,
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dev->io_base + SMI_CR2);
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/* wait for tff */
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ret = wait_event_interruptible_timeout(dev->cmd_complete,
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dev->status & TFF, SMI_CMD_TIMEOUT);
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/* copy dev->status (lower 16 bits) in order to release lock */
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if (ret > 0)
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ret = dev->status & 0xffff;
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else if (ret == 0)
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ret = -ETIMEDOUT;
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/* restore the ctrl regs state */
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writel(ctrlreg1, dev->io_base + SMI_CR1);
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writel(0, dev->io_base + SMI_CR2);
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mutex_unlock(&dev->lock);
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return ret;
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}
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/**
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* spear_smi_wait_till_ready - wait till flash is ready
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* @dev: structure of SMI information.
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* @bank: flash corresponding to this bank
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* @timeout: timeout for busy wait condition
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*
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* This routine checks for WIP (write in progress) bit in Status register
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* If successful the routine returns 0 else -EBUSY
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*/
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static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank,
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unsigned long timeout)
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{
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unsigned long finish;
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int status;
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finish = jiffies + timeout;
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do {
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status = spear_smi_read_sr(dev, bank);
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if (status < 0) {
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if (status == -ETIMEDOUT)
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continue; /* try till finish */
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return status;
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} else if (!(status & SR_WIP)) {
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return 0;
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}
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cond_resched();
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} while (!time_after_eq(jiffies, finish));
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dev_err(&dev->pdev->dev, "smi controller is busy, timeout\n");
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return -EBUSY;
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}
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/**
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* spear_smi_int_handler - SMI Interrupt Handler.
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* @irq: irq number
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* @dev_id: structure of SMI device, embedded in dev_id.
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*
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* The handler clears all interrupt conditions and records the status in
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* dev->status which is used by the driver later.
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*/
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static irqreturn_t spear_smi_int_handler(int irq, void *dev_id)
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{
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u32 status = 0;
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struct spear_smi *dev = dev_id;
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status = readl(dev->io_base + SMI_SR);
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if (unlikely(!status))
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return IRQ_NONE;
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/* clear all interrupt conditions */
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writel(0, dev->io_base + SMI_SR);
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/* copy the status register in dev->status */
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dev->status |= status;
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/* send the completion */
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wake_up_interruptible(&dev->cmd_complete);
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return IRQ_HANDLED;
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}
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/**
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* spear_smi_hw_init - initializes the smi controller.
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* @dev: structure of smi device
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*
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* this routine initializes the smi controller wit the default values
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*/
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static void spear_smi_hw_init(struct spear_smi *dev)
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{
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unsigned long rate = 0;
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u32 prescale = 0;
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u32 val;
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rate = clk_get_rate(dev->clk);
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/* functional clock of smi */
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prescale = DIV_ROUND_UP(rate, dev->clk_rate);
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/*
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* setting the standard values, fast mode, prescaler for
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* SMI_MAX_CLOCK_FREQ (50MHz) operation and bank enable
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*/
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val = HOLD1 | BANK_EN | DSEL_TIME | (prescale << 8);
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mutex_lock(&dev->lock);
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/* clear all interrupt conditions */
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writel(0, dev->io_base + SMI_SR);
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writel(val, dev->io_base + SMI_CR1);
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mutex_unlock(&dev->lock);
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}
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/**
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* get_flash_index - match chip id from a flash list.
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* @flash_id: a valid nor flash chip id obtained from board.
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*
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* try to validate the chip id by matching from a list, if not found then simply
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* returns negative. In case of success returns index in to the flash devices
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* array.
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*/
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static int get_flash_index(u32 flash_id)
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{
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int index;
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/* Matches chip-id to entire list of 'serial-nor flash' ids */
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for (index = 0; index < ARRAY_SIZE(flash_devices); index++) {
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if (flash_devices[index].device_id == flash_id)
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return index;
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}
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/* Memory chip is not listed and not supported */
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return -ENODEV;
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}
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/**
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* spear_smi_write_enable - Enable the flash to do write operation
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* @dev: structure of SMI device
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* @bank: enable write for flash connected to this bank
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*
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* Set write enable latch with Write Enable command.
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* Returns 0 on success.
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*/
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static int spear_smi_write_enable(struct spear_smi *dev, u32 bank)
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{
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int ret;
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u32 ctrlreg1;
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mutex_lock(&dev->lock);
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dev->status = 0; /* Will be set in interrupt handler */
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ctrlreg1 = readl(dev->io_base + SMI_CR1);
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/* program smi in h/w mode */
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writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);
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/* give the flash, write enable command */
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writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);
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ret = wait_event_interruptible_timeout(dev->cmd_complete,
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dev->status & TFF, SMI_CMD_TIMEOUT);
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/* restore the ctrl regs state */
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writel(ctrlreg1, dev->io_base + SMI_CR1);
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writel(0, dev->io_base + SMI_CR2);
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if (ret == 0) {
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ret = -EIO;
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dev_err(&dev->pdev->dev,
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"smi controller failed on write enable\n");
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} else if (ret > 0) {
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/* check whether write mode status is set for required bank */
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if (dev->status & (1 << (bank + WM_SHIFT)))
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ret = 0;
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else {
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dev_err(&dev->pdev->dev, "couldn't enable write\n");
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ret = -EIO;
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}
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}
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mutex_unlock(&dev->lock);
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return ret;
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}
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static inline u32
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get_sector_erase_cmd(struct spear_snor_flash *flash, u32 offset)
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{
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u32 cmd;
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u8 *x = (u8 *)&cmd;
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x[0] = flash->erase_cmd;
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x[1] = offset >> 16;
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x[2] = offset >> 8;
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x[3] = offset;
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return cmd;
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}
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/**
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* spear_smi_erase_sector - erase one sector of flash
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* @dev: structure of SMI information
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* @command: erase command to be send
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* @bank: bank to which this command needs to be send
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* @bytes: size of command
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*
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* Erase one sector of flash memory at offset ``offset'' which is any
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* address within the sector which should be erased.
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* Returns 0 if successful, non-zero otherwise.
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*/
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static int spear_smi_erase_sector(struct spear_smi *dev,
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u32 bank, u32 command, u32 bytes)
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{
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u32 ctrlreg1 = 0;
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int ret;
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ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
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if (ret)
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return ret;
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ret = spear_smi_write_enable(dev, bank);
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if (ret)
|
|
return ret;
|
|
|
|
mutex_lock(&dev->lock);
|
|
|
|
ctrlreg1 = readl(dev->io_base + SMI_CR1);
|
|
writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);
|
|
|
|
/* send command in sw mode */
|
|
writel(command, dev->io_base + SMI_TR);
|
|
|
|
writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),
|
|
dev->io_base + SMI_CR2);
|
|
|
|
ret = wait_event_interruptible_timeout(dev->cmd_complete,
|
|
dev->status & TFF, SMI_CMD_TIMEOUT);
|
|
|
|
if (ret == 0) {
|
|
ret = -EIO;
|
|
dev_err(&dev->pdev->dev, "sector erase failed\n");
|
|
} else if (ret > 0)
|
|
ret = 0; /* success */
|
|
|
|
/* restore ctrl regs */
|
|
writel(ctrlreg1, dev->io_base + SMI_CR1);
|
|
writel(0, dev->io_base + SMI_CR2);
|
|
|
|
mutex_unlock(&dev->lock);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* spear_mtd_erase - perform flash erase operation as requested by user
|
|
* @mtd: Provides the memory characteristics
|
|
* @e_info: Provides the erase information
|
|
*
|
|
* Erase an address range on the flash chip. The address range may extend
|
|
* one or more erase sectors. Return an error is there is a problem erasing.
|
|
*/
|
|
static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info)
|
|
{
|
|
struct spear_snor_flash *flash = get_flash_data(mtd);
|
|
struct spear_smi *dev = mtd->priv;
|
|
u32 addr, command, bank;
|
|
int len, ret;
|
|
|
|
if (!flash || !dev)
|
|
return -ENODEV;
|
|
|
|
bank = flash->bank;
|
|
if (bank > dev->num_flashes - 1) {
|
|
dev_err(&dev->pdev->dev, "Invalid Bank Num");
|
|
return -EINVAL;
|
|
}
|
|
|
|
addr = e_info->addr;
|
|
len = e_info->len;
|
|
|
|
mutex_lock(&flash->lock);
|
|
|
|
/* now erase sectors in loop */
|
|
while (len) {
|
|
command = get_sector_erase_cmd(flash, addr);
|
|
/* preparing the command for flash */
|
|
ret = spear_smi_erase_sector(dev, bank, command, 4);
|
|
if (ret) {
|
|
mutex_unlock(&flash->lock);
|
|
return ret;
|
|
}
|
|
addr += mtd->erasesize;
|
|
len -= mtd->erasesize;
|
|
}
|
|
|
|
mutex_unlock(&flash->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* spear_mtd_read - performs flash read operation as requested by the user
|
|
* @mtd: MTD information of the memory bank
|
|
* @from: Address from which to start read
|
|
* @len: Number of bytes to be read
|
|
* @retlen: Fills the Number of bytes actually read
|
|
* @buf: Fills this after reading
|
|
*
|
|
* Read an address range from the flash chip. The address range
|
|
* may be any size provided it is within the physical boundaries.
|
|
* Returns 0 on success, non zero otherwise
|
|
*/
|
|
static int spear_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|
size_t *retlen, u8 *buf)
|
|
{
|
|
struct spear_snor_flash *flash = get_flash_data(mtd);
|
|
struct spear_smi *dev = mtd->priv;
|
|
void __iomem *src;
|
|
u32 ctrlreg1, val;
|
|
int ret;
|
|
|
|
if (!flash || !dev)
|
|
return -ENODEV;
|
|
|
|
if (flash->bank > dev->num_flashes - 1) {
|
|
dev_err(&dev->pdev->dev, "Invalid Bank Num");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* select address as per bank number */
|
|
src = flash->base_addr + from;
|
|
|
|
mutex_lock(&flash->lock);
|
|
|
|
/* wait till previous write/erase is done. */
|
|
ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT);
|
|
if (ret) {
|
|
mutex_unlock(&flash->lock);
|
|
return ret;
|
|
}
|
|
|
|
mutex_lock(&dev->lock);
|
|
/* put smi in hw mode not wbt mode */
|
|
ctrlreg1 = val = readl(dev->io_base + SMI_CR1);
|
|
val &= ~(SW_MODE | WB_MODE);
|
|
if (flash->fast_mode)
|
|
val |= FAST_MODE;
|
|
|
|
writel(val, dev->io_base + SMI_CR1);
|
|
|
|
memcpy_fromio(buf, src, len);
|
|
|
|
/* restore ctrl reg1 */
|
|
writel(ctrlreg1, dev->io_base + SMI_CR1);
|
|
mutex_unlock(&dev->lock);
|
|
|
|
*retlen = len;
|
|
mutex_unlock(&flash->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* The purpose of this function is to ensure a memcpy_toio() with byte writes
|
|
* only. Its structure is inspired from the ARM implementation of _memcpy_toio()
|
|
* which also does single byte writes but cannot be used here as this is just an
|
|
* implementation detail and not part of the API. Not mentioning the comment
|
|
* stating that _memcpy_toio() should be optimized.
|
|
*/
|
|
static void spear_smi_memcpy_toio_b(volatile void __iomem *dest,
|
|
const void *src, size_t len)
|
|
{
|
|
const unsigned char *from = src;
|
|
|
|
while (len) {
|
|
len--;
|
|
writeb(*from, dest);
|
|
from++;
|
|
dest++;
|
|
}
|
|
}
|
|
|
|
static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank,
|
|
void __iomem *dest, const void *src, size_t len)
|
|
{
|
|
int ret;
|
|
u32 ctrlreg1;
|
|
|
|
/* wait until finished previous write command. */
|
|
ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* put smi in write enable */
|
|
ret = spear_smi_write_enable(dev, bank);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* put smi in hw, write burst mode */
|
|
mutex_lock(&dev->lock);
|
|
|
|
ctrlreg1 = readl(dev->io_base + SMI_CR1);
|
|
writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);
|
|
|
|
/*
|
|
* In Write Burst mode (WB_MODE), the specs states that writes must be:
|
|
* - incremental
|
|
* - of the same size
|
|
* The ARM implementation of memcpy_toio() will optimize the number of
|
|
* I/O by using as much 4-byte writes as possible, surrounded by
|
|
* 2-byte/1-byte access if:
|
|
* - the destination is not 4-byte aligned
|
|
* - the length is not a multiple of 4-byte.
|
|
* Avoid this alternance of write access size by using our own 'byte
|
|
* access' helper if at least one of the two conditions above is true.
|
|
*/
|
|
if (IS_ALIGNED(len, sizeof(u32)) &&
|
|
IS_ALIGNED((uintptr_t)dest, sizeof(u32)))
|
|
memcpy_toio(dest, src, len);
|
|
else
|
|
spear_smi_memcpy_toio_b(dest, src, len);
|
|
|
|
writel(ctrlreg1, dev->io_base + SMI_CR1);
|
|
|
|
mutex_unlock(&dev->lock);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* spear_mtd_write - performs write operation as requested by the user.
|
|
* @mtd: MTD information of the memory bank.
|
|
* @to: Address to write.
|
|
* @len: Number of bytes to be written.
|
|
* @retlen: Number of bytes actually wrote.
|
|
* @buf: Buffer from which the data to be taken.
|
|
*
|
|
* Write an address range to the flash chip. Data must be written in
|
|
* flash_page_size chunks. The address range may be any size provided
|
|
* it is within the physical boundaries.
|
|
* Returns 0 on success, non zero otherwise
|
|
*/
|
|
static int spear_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
|
|
size_t *retlen, const u8 *buf)
|
|
{
|
|
struct spear_snor_flash *flash = get_flash_data(mtd);
|
|
struct spear_smi *dev = mtd->priv;
|
|
void __iomem *dest;
|
|
u32 page_offset, page_size;
|
|
int ret;
|
|
|
|
if (!flash || !dev)
|
|
return -ENODEV;
|
|
|
|
if (flash->bank > dev->num_flashes - 1) {
|
|
dev_err(&dev->pdev->dev, "Invalid Bank Num");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* select address as per bank number */
|
|
dest = flash->base_addr + to;
|
|
mutex_lock(&flash->lock);
|
|
|
|
page_offset = (u32)to % flash->page_size;
|
|
|
|
/* do if all the bytes fit onto one page */
|
|
if (page_offset + len <= flash->page_size) {
|
|
ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len);
|
|
if (!ret)
|
|
*retlen += len;
|
|
} else {
|
|
u32 i;
|
|
|
|
/* the size of data remaining on the first page */
|
|
page_size = flash->page_size - page_offset;
|
|
|
|
ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf,
|
|
page_size);
|
|
if (ret)
|
|
goto err_write;
|
|
else
|
|
*retlen += page_size;
|
|
|
|
/* write everything in pagesize chunks */
|
|
for (i = page_size; i < len; i += page_size) {
|
|
page_size = len - i;
|
|
if (page_size > flash->page_size)
|
|
page_size = flash->page_size;
|
|
|
|
ret = spear_smi_cpy_toio(dev, flash->bank, dest + i,
|
|
buf + i, page_size);
|
|
if (ret)
|
|
break;
|
|
else
|
|
*retlen += page_size;
|
|
}
|
|
}
|
|
|
|
err_write:
|
|
mutex_unlock(&flash->lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* spear_smi_probe_flash - Detects the NOR Flash chip.
|
|
* @dev: structure of SMI information.
|
|
* @bank: bank on which flash must be probed
|
|
*
|
|
* This routine will check whether there exists a flash chip on a given memory
|
|
* bank ID.
|
|
* Return index of the probed flash in flash devices structure
|
|
*/
|
|
static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank)
|
|
{
|
|
int ret;
|
|
u32 val = 0;
|
|
|
|
ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mutex_lock(&dev->lock);
|
|
|
|
dev->status = 0; /* Will be set in interrupt handler */
|
|
/* put smi in sw mode */
|
|
val = readl(dev->io_base + SMI_CR1);
|
|
writel(val | SW_MODE, dev->io_base + SMI_CR1);
|
|
|
|
/* send readid command in sw mode */
|
|
writel(OPCODE_RDID, dev->io_base + SMI_TR);
|
|
|
|
val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) |
|
|
(3 << RX_LEN_SHIFT) | TFIE;
|
|
writel(val, dev->io_base + SMI_CR2);
|
|
|
|
/* wait for TFF */
|
|
ret = wait_event_interruptible_timeout(dev->cmd_complete,
|
|
dev->status & TFF, SMI_CMD_TIMEOUT);
|
|
if (ret <= 0) {
|
|
ret = -ENODEV;
|
|
goto err_probe;
|
|
}
|
|
|
|
/* get memory chip id */
|
|
val = readl(dev->io_base + SMI_RR);
|
|
val &= 0x00ffffff;
|
|
ret = get_flash_index(val);
|
|
|
|
err_probe:
|
|
/* clear sw mode */
|
|
val = readl(dev->io_base + SMI_CR1);
|
|
writel(val & ~SW_MODE, dev->io_base + SMI_CR1);
|
|
|
|
mutex_unlock(&dev->lock);
|
|
return ret;
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_OF
|
|
static int spear_smi_probe_config_dt(struct platform_device *pdev,
|
|
struct device_node *np)
|
|
{
|
|
struct spear_smi_plat_data *pdata = dev_get_platdata(&pdev->dev);
|
|
struct device_node *pp;
|
|
const __be32 *addr;
|
|
u32 val;
|
|
int len;
|
|
int i = 0;
|
|
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
of_property_read_u32(np, "clock-rate", &val);
|
|
pdata->clk_rate = val;
|
|
|
|
pdata->board_flash_info = devm_kzalloc(&pdev->dev,
|
|
sizeof(*pdata->board_flash_info),
|
|
GFP_KERNEL);
|
|
if (!pdata->board_flash_info)
|
|
return -ENOMEM;
|
|
|
|
/* Fill structs for each subnode (flash device) */
|
|
for_each_child_of_node(np, pp) {
|
|
pdata->np[i] = pp;
|
|
|
|
/* Read base-addr and size from DT */
|
|
addr = of_get_property(pp, "reg", &len);
|
|
pdata->board_flash_info->mem_base = be32_to_cpup(&addr[0]);
|
|
pdata->board_flash_info->size = be32_to_cpup(&addr[1]);
|
|
|
|
if (of_get_property(pp, "st,smi-fast-mode", NULL))
|
|
pdata->board_flash_info->fast_mode = 1;
|
|
|
|
i++;
|
|
}
|
|
|
|
pdata->num_flashes = i;
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int spear_smi_probe_config_dt(struct platform_device *pdev,
|
|
struct device_node *np)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
#endif
|
|
|
|
static int spear_smi_setup_banks(struct platform_device *pdev,
|
|
u32 bank, struct device_node *np)
|
|
{
|
|
struct spear_smi *dev = platform_get_drvdata(pdev);
|
|
struct spear_smi_flash_info *flash_info;
|
|
struct spear_smi_plat_data *pdata;
|
|
struct spear_snor_flash *flash;
|
|
struct mtd_partition *parts = NULL;
|
|
int count = 0;
|
|
int flash_index;
|
|
int ret = 0;
|
|
|
|
pdata = dev_get_platdata(&pdev->dev);
|
|
if (bank > pdata->num_flashes - 1)
|
|
return -EINVAL;
|
|
|
|
flash_info = &pdata->board_flash_info[bank];
|
|
if (!flash_info)
|
|
return -ENODEV;
|
|
|
|
flash = devm_kzalloc(&pdev->dev, sizeof(*flash), GFP_ATOMIC);
|
|
if (!flash)
|
|
return -ENOMEM;
|
|
flash->bank = bank;
|
|
flash->fast_mode = flash_info->fast_mode ? 1 : 0;
|
|
mutex_init(&flash->lock);
|
|
|
|
/* verify whether nor flash is really present on board */
|
|
flash_index = spear_smi_probe_flash(dev, bank);
|
|
if (flash_index < 0) {
|
|
dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank);
|
|
return flash_index;
|
|
}
|
|
/* map the memory for nor flash chip */
|
|
flash->base_addr = devm_ioremap(&pdev->dev, flash_info->mem_base,
|
|
flash_info->size);
|
|
if (!flash->base_addr)
|
|
return -EIO;
|
|
|
|
dev->flash[bank] = flash;
|
|
flash->mtd.priv = dev;
|
|
|
|
if (flash_info->name)
|
|
flash->mtd.name = flash_info->name;
|
|
else
|
|
flash->mtd.name = flash_devices[flash_index].name;
|
|
|
|
flash->mtd.dev.parent = &pdev->dev;
|
|
mtd_set_of_node(&flash->mtd, np);
|
|
flash->mtd.type = MTD_NORFLASH;
|
|
flash->mtd.writesize = 1;
|
|
flash->mtd.flags = MTD_CAP_NORFLASH;
|
|
flash->mtd.size = flash_info->size;
|
|
flash->mtd.erasesize = flash_devices[flash_index].sectorsize;
|
|
flash->page_size = flash_devices[flash_index].pagesize;
|
|
flash->mtd.writebufsize = flash->page_size;
|
|
flash->erase_cmd = flash_devices[flash_index].erase_cmd;
|
|
flash->mtd._erase = spear_mtd_erase;
|
|
flash->mtd._read = spear_mtd_read;
|
|
flash->mtd._write = spear_mtd_write;
|
|
flash->dev_id = flash_devices[flash_index].device_id;
|
|
|
|
dev_info(&dev->pdev->dev, "mtd .name=%s .size=%llx(%lluM)\n",
|
|
flash->mtd.name, flash->mtd.size,
|
|
flash->mtd.size / (1024 * 1024));
|
|
|
|
dev_info(&dev->pdev->dev, ".erasesize = 0x%x(%uK)\n",
|
|
flash->mtd.erasesize, flash->mtd.erasesize / 1024);
|
|
|
|
#ifndef CONFIG_OF
|
|
if (flash_info->partitions) {
|
|
parts = flash_info->partitions;
|
|
count = flash_info->nr_partitions;
|
|
}
|
|
#endif
|
|
|
|
ret = mtd_device_register(&flash->mtd, parts, count);
|
|
if (ret) {
|
|
dev_err(&dev->pdev->dev, "Err MTD partition=%d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* spear_smi_probe - Entry routine
|
|
* @pdev: platform device structure
|
|
*
|
|
* This is the first routine which gets invoked during booting and does all
|
|
* initialization/allocation work. The routine looks for available memory banks,
|
|
* and do proper init for any found one.
|
|
* Returns 0 on success, non zero otherwise
|
|
*/
|
|
static int spear_smi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct spear_smi_plat_data *pdata = NULL;
|
|
struct spear_smi *dev;
|
|
struct resource *smi_base;
|
|
int irq, ret = 0;
|
|
int i;
|
|
|
|
if (np) {
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
pdev->dev.platform_data = pdata;
|
|
ret = spear_smi_probe_config_dt(pdev, np);
|
|
if (ret) {
|
|
ret = -ENODEV;
|
|
dev_err(&pdev->dev, "no platform data\n");
|
|
goto err;
|
|
}
|
|
} else {
|
|
pdata = dev_get_platdata(&pdev->dev);
|
|
if (!pdata) {
|
|
ret = -ENODEV;
|
|
dev_err(&pdev->dev, "no platform data\n");
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
|
|
if (!dev) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
dev->io_base = devm_ioremap_resource(&pdev->dev, smi_base);
|
|
if (IS_ERR(dev->io_base)) {
|
|
ret = PTR_ERR(dev->io_base);
|
|
goto err;
|
|
}
|
|
|
|
dev->pdev = pdev;
|
|
dev->clk_rate = pdata->clk_rate;
|
|
|
|
if (dev->clk_rate > SMI_MAX_CLOCK_FREQ)
|
|
dev->clk_rate = SMI_MAX_CLOCK_FREQ;
|
|
|
|
dev->num_flashes = pdata->num_flashes;
|
|
|
|
if (dev->num_flashes > MAX_NUM_FLASH_CHIP) {
|
|
dev_err(&pdev->dev, "exceeding max number of flashes\n");
|
|
dev->num_flashes = MAX_NUM_FLASH_CHIP;
|
|
}
|
|
|
|
dev->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(dev->clk)) {
|
|
ret = PTR_ERR(dev->clk);
|
|
goto err;
|
|
}
|
|
|
|
ret = clk_prepare_enable(dev->clk);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, spear_smi_int_handler, 0,
|
|
pdev->name, dev);
|
|
if (ret) {
|
|
dev_err(&dev->pdev->dev, "SMI IRQ allocation failed\n");
|
|
goto err_irq;
|
|
}
|
|
|
|
mutex_init(&dev->lock);
|
|
init_waitqueue_head(&dev->cmd_complete);
|
|
spear_smi_hw_init(dev);
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
/* loop for each serial nor-flash which is connected to smi */
|
|
for (i = 0; i < dev->num_flashes; i++) {
|
|
ret = spear_smi_setup_banks(pdev, i, pdata->np[i]);
|
|
if (ret) {
|
|
dev_err(&dev->pdev->dev, "bank setup failed\n");
|
|
goto err_irq;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_irq:
|
|
clk_disable_unprepare(dev->clk);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* spear_smi_remove - Exit routine
|
|
* @pdev: platform device structure
|
|
*
|
|
* free all allocations and delete the partitions.
|
|
*/
|
|
static int spear_smi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spear_smi *dev;
|
|
struct spear_snor_flash *flash;
|
|
int i;
|
|
|
|
dev = platform_get_drvdata(pdev);
|
|
|
|
/* clean up for all nor flash */
|
|
for (i = 0; i < dev->num_flashes; i++) {
|
|
flash = dev->flash[i];
|
|
if (!flash)
|
|
continue;
|
|
|
|
/* clean up mtd stuff */
|
|
WARN_ON(mtd_device_unregister(&flash->mtd));
|
|
}
|
|
|
|
clk_disable_unprepare(dev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int spear_smi_suspend(struct device *dev)
|
|
{
|
|
struct spear_smi *sdev = dev_get_drvdata(dev);
|
|
|
|
if (sdev && sdev->clk)
|
|
clk_disable_unprepare(sdev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spear_smi_resume(struct device *dev)
|
|
{
|
|
struct spear_smi *sdev = dev_get_drvdata(dev);
|
|
int ret = -EPERM;
|
|
|
|
if (sdev && sdev->clk)
|
|
ret = clk_prepare_enable(sdev->clk);
|
|
|
|
if (!ret)
|
|
spear_smi_hw_init(sdev);
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(spear_smi_pm_ops, spear_smi_suspend, spear_smi_resume);
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id spear_smi_id_table[] = {
|
|
{ .compatible = "st,spear600-smi" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, spear_smi_id_table);
|
|
#endif
|
|
|
|
static struct platform_driver spear_smi_driver = {
|
|
.driver = {
|
|
.name = "smi",
|
|
.bus = &platform_bus_type,
|
|
.of_match_table = of_match_ptr(spear_smi_id_table),
|
|
.pm = &spear_smi_pm_ops,
|
|
},
|
|
.probe = spear_smi_probe,
|
|
.remove = spear_smi_remove,
|
|
};
|
|
module_platform_driver(spear_smi_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Ashish Priyadarshi, Shiraz Hashim <shiraz.linux.kernel@gmail.com>");
|
|
MODULE_DESCRIPTION("MTD SMI driver for serial nor flash chips");
|