263 lines
6.2 KiB
C
263 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* NAND Flash Controller Device Driver for DT
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*
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* Copyright © 2011, Picochip.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "denali.h"
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struct denali_dt {
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struct denali_controller controller;
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struct clk *clk; /* core clock */
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struct clk *clk_x; /* bus interface clock */
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struct clk *clk_ecc; /* ECC circuit clock */
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struct reset_control *rst; /* core reset */
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struct reset_control *rst_reg; /* register reset */
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};
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struct denali_dt_data {
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unsigned int revision;
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unsigned int caps;
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unsigned int oob_skip_bytes;
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const struct nand_ecc_caps *ecc_caps;
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};
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NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
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512, 8, 15);
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static const struct denali_dt_data denali_socfpga_data = {
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.caps = DENALI_CAP_HW_ECC_FIXUP,
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.oob_skip_bytes = 2,
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.ecc_caps = &denali_socfpga_ecc_caps,
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};
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NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
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1024, 8, 16, 24);
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static const struct denali_dt_data denali_uniphier_v5a_data = {
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.caps = DENALI_CAP_HW_ECC_FIXUP |
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DENALI_CAP_DMA_64BIT,
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.oob_skip_bytes = 8,
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.ecc_caps = &denali_uniphier_v5a_ecc_caps,
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};
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NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
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1024, 8, 16);
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static const struct denali_dt_data denali_uniphier_v5b_data = {
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.revision = 0x0501,
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.caps = DENALI_CAP_HW_ECC_FIXUP |
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DENALI_CAP_DMA_64BIT,
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.oob_skip_bytes = 8,
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.ecc_caps = &denali_uniphier_v5b_ecc_caps,
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};
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static const struct of_device_id denali_nand_dt_ids[] = {
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{
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.compatible = "altr,socfpga-denali-nand",
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.data = &denali_socfpga_data,
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},
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{
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.compatible = "socionext,uniphier-denali-nand-v5a",
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.data = &denali_uniphier_v5a_data,
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},
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{
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.compatible = "socionext,uniphier-denali-nand-v5b",
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.data = &denali_uniphier_v5b_data,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
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static int denali_dt_chip_init(struct denali_controller *denali,
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struct device_node *chip_np)
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{
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struct denali_chip *dchip;
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u32 bank;
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int nsels, i, ret;
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nsels = of_property_count_u32_elems(chip_np, "reg");
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if (nsels < 0)
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return nsels;
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dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
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GFP_KERNEL);
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if (!dchip)
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return -ENOMEM;
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dchip->nsels = nsels;
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for (i = 0; i < nsels; i++) {
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ret = of_property_read_u32_index(chip_np, "reg", i, &bank);
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if (ret)
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return ret;
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dchip->sels[i].bank = bank;
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nand_set_flash_node(&dchip->chip, chip_np);
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}
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return denali_chip_init(denali, dchip);
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}
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static int denali_dt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct denali_dt *dt;
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const struct denali_dt_data *data;
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struct denali_controller *denali;
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struct device_node *np;
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int ret;
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dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
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if (!dt)
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return -ENOMEM;
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denali = &dt->controller;
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data = of_device_get_match_data(dev);
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if (WARN_ON(!data))
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return -EINVAL;
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denali->revision = data->revision;
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denali->caps = data->caps;
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denali->oob_skip_bytes = data->oob_skip_bytes;
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denali->ecc_caps = data->ecc_caps;
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denali->dev = dev;
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denali->irq = platform_get_irq(pdev, 0);
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if (denali->irq < 0)
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return denali->irq;
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denali->reg = devm_platform_ioremap_resource_byname(pdev, "denali_reg");
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if (IS_ERR(denali->reg))
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return PTR_ERR(denali->reg);
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denali->host = devm_platform_ioremap_resource_byname(pdev, "nand_data");
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if (IS_ERR(denali->host))
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return PTR_ERR(denali->host);
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dt->clk = devm_clk_get(dev, "nand");
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if (IS_ERR(dt->clk))
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return PTR_ERR(dt->clk);
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dt->clk_x = devm_clk_get(dev, "nand_x");
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if (IS_ERR(dt->clk_x))
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return PTR_ERR(dt->clk_x);
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dt->clk_ecc = devm_clk_get(dev, "ecc");
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if (IS_ERR(dt->clk_ecc))
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return PTR_ERR(dt->clk_ecc);
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dt->rst = devm_reset_control_get_optional_shared(dev, "nand");
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if (IS_ERR(dt->rst))
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return PTR_ERR(dt->rst);
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dt->rst_reg = devm_reset_control_get_optional_shared(dev, "reg");
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if (IS_ERR(dt->rst_reg))
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return PTR_ERR(dt->rst_reg);
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ret = clk_prepare_enable(dt->clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(dt->clk_x);
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if (ret)
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goto out_disable_clk;
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ret = clk_prepare_enable(dt->clk_ecc);
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if (ret)
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goto out_disable_clk_x;
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denali->clk_rate = clk_get_rate(dt->clk);
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denali->clk_x_rate = clk_get_rate(dt->clk_x);
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/*
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* Deassert the register reset, and the core reset in this order.
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* Deasserting the core reset while the register reset is asserted
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* will cause unpredictable behavior in the controller.
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*/
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ret = reset_control_deassert(dt->rst_reg);
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if (ret)
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goto out_disable_clk_ecc;
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ret = reset_control_deassert(dt->rst);
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if (ret)
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goto out_assert_rst_reg;
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/*
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* When the reset is deasserted, the initialization sequence is kicked
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* (bootstrap process). The driver must wait until it finished.
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* Otherwise, it will result in unpredictable behavior.
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*/
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usleep_range(200, 1000);
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ret = denali_init(denali);
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if (ret)
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goto out_assert_rst;
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for_each_child_of_node(dev->of_node, np) {
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ret = denali_dt_chip_init(denali, np);
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if (ret) {
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of_node_put(np);
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goto out_remove_denali;
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}
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}
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platform_set_drvdata(pdev, dt);
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return 0;
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out_remove_denali:
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denali_remove(denali);
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out_assert_rst:
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reset_control_assert(dt->rst);
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out_assert_rst_reg:
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reset_control_assert(dt->rst_reg);
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out_disable_clk_ecc:
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clk_disable_unprepare(dt->clk_ecc);
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out_disable_clk_x:
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clk_disable_unprepare(dt->clk_x);
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out_disable_clk:
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clk_disable_unprepare(dt->clk);
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return ret;
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}
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static int denali_dt_remove(struct platform_device *pdev)
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{
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struct denali_dt *dt = platform_get_drvdata(pdev);
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denali_remove(&dt->controller);
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reset_control_assert(dt->rst);
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reset_control_assert(dt->rst_reg);
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clk_disable_unprepare(dt->clk_ecc);
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clk_disable_unprepare(dt->clk_x);
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clk_disable_unprepare(dt->clk);
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return 0;
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}
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static struct platform_driver denali_dt_driver = {
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.probe = denali_dt_probe,
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.remove = denali_dt_remove,
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.driver = {
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.name = "denali-nand-dt",
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.of_match_table = denali_nand_dt_ids,
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},
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};
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module_platform_driver(denali_dt_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Jamie Iles");
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MODULE_DESCRIPTION("DT driver for Denali NAND controller");
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