335 lines
8.4 KiB
C
335 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2017 Free Electrons
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* Copyright (C) 2017 NextThing Co
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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*/
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#include "linux/delay.h"
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#include "internals.h"
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#define MACRONIX_READ_RETRY_BIT BIT(0)
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#define MACRONIX_NUM_READ_RETRY_MODES 6
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#define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0
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#define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38
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#define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0
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#define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0
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#define MACRONIX_RANDOMIZER_BIT BIT(1)
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#define MACRONIX_RANDOMIZER_ENPGM BIT(0)
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#define MACRONIX_RANDOMIZER_RANDEN BIT(1)
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#define MACRONIX_RANDOMIZER_RANDOPT BIT(2)
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#define MACRONIX_RANDOMIZER_MODE_ENTER \
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(MACRONIX_RANDOMIZER_ENPGM | \
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MACRONIX_RANDOMIZER_RANDEN | \
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MACRONIX_RANDOMIZER_RANDOPT)
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#define MACRONIX_RANDOMIZER_MODE_EXIT \
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(MACRONIX_RANDOMIZER_RANDEN | \
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MACRONIX_RANDOMIZER_RANDOPT)
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#define MXIC_CMD_POWER_DOWN 0xB9
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struct nand_onfi_vendor_macronix {
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u8 reserved;
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u8 reliability_func;
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} __packed;
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static int macronix_nand_setup_read_retry(struct nand_chip *chip, int mode)
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{
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u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
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if (!chip->parameters.supports_set_get_features ||
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!test_bit(ONFI_FEATURE_ADDR_READ_RETRY,
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chip->parameters.set_feature_list))
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return -ENOTSUPP;
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feature[0] = mode;
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return nand_set_features(chip, ONFI_FEATURE_ADDR_READ_RETRY, feature);
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}
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static int macronix_nand_randomizer_check_enable(struct nand_chip *chip)
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{
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u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
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int ret;
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ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
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feature);
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if (ret < 0)
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return ret;
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if (feature[0])
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return feature[0];
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feature[0] = MACRONIX_RANDOMIZER_MODE_ENTER;
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ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
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feature);
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if (ret < 0)
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return ret;
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/* RANDEN and RANDOPT OTP bits are programmed */
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feature[0] = 0x0;
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ret = nand_prog_page_op(chip, 0, 0, feature, 1);
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if (ret < 0)
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return ret;
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ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
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feature);
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if (ret < 0)
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return ret;
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feature[0] &= MACRONIX_RANDOMIZER_MODE_EXIT;
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ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
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feature);
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if (ret < 0)
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return ret;
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return 0;
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}
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static void macronix_nand_onfi_init(struct nand_chip *chip)
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{
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struct nand_parameters *p = &chip->parameters;
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struct nand_onfi_vendor_macronix *mxic;
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struct device_node *dn = nand_get_flash_node(chip);
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int rand_otp = 0;
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int ret;
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if (!p->onfi)
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return;
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if (of_find_property(dn, "mxic,enable-randomizer-otp", NULL))
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rand_otp = 1;
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mxic = (struct nand_onfi_vendor_macronix *)p->onfi->vendor;
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/* Subpage write is prohibited in randomizer operatoin */
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if (rand_otp && chip->options & NAND_NO_SUBPAGE_WRITE &&
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mxic->reliability_func & MACRONIX_RANDOMIZER_BIT) {
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if (p->supports_set_get_features) {
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bitmap_set(p->set_feature_list,
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ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1);
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bitmap_set(p->get_feature_list,
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ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1);
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ret = macronix_nand_randomizer_check_enable(chip);
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if (ret < 0) {
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bitmap_clear(p->set_feature_list,
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ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
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1);
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bitmap_clear(p->get_feature_list,
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ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
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1);
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pr_info("Macronix NAND randomizer failed\n");
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} else {
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pr_info("Macronix NAND randomizer enabled\n");
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}
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}
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}
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if ((mxic->reliability_func & MACRONIX_READ_RETRY_BIT) == 0)
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return;
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chip->read_retries = MACRONIX_NUM_READ_RETRY_MODES;
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chip->ops.setup_read_retry = macronix_nand_setup_read_retry;
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if (p->supports_set_get_features) {
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bitmap_set(p->set_feature_list,
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ONFI_FEATURE_ADDR_READ_RETRY, 1);
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bitmap_set(p->get_feature_list,
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ONFI_FEATURE_ADDR_READ_RETRY, 1);
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}
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}
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/*
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* Macronix AC series does not support using SET/GET_FEATURES to change
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* the timings unlike what is declared in the parameter page. Unflag
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* this feature to avoid unnecessary downturns.
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*/
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static void macronix_nand_fix_broken_get_timings(struct nand_chip *chip)
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{
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int i;
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static const char * const broken_get_timings[] = {
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"MX30LF1G18AC",
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"MX30LF1G28AC",
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"MX30LF2G18AC",
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"MX30LF2G28AC",
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"MX30LF4G18AC",
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"MX30LF4G28AC",
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"MX60LF8G18AC",
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"MX30UF1G18AC",
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"MX30UF1G16AC",
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"MX30UF2G18AC",
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"MX30UF2G16AC",
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"MX30UF4G18AC",
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"MX30UF4G16AC",
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"MX30UF4G28AC",
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};
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if (!chip->parameters.supports_set_get_features)
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return;
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i = match_string(broken_get_timings, ARRAY_SIZE(broken_get_timings),
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chip->parameters.model);
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if (i < 0)
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return;
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bitmap_clear(chip->parameters.get_feature_list,
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ONFI_FEATURE_ADDR_TIMING_MODE, 1);
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bitmap_clear(chip->parameters.set_feature_list,
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ONFI_FEATURE_ADDR_TIMING_MODE, 1);
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}
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/*
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* Macronix NAND supports Block Protection by Protectoin(PT) pin;
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* active high at power-on which protects the entire chip even the #WP is
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* disabled. Lock/unlock protection area can be partition according to
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* protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
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*/
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static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
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{
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u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
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int ret;
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feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
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nand_select_target(chip, 0);
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ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
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feature);
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nand_deselect_target(chip);
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if (ret)
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pr_err("%s all blocks failed\n", __func__);
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return ret;
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}
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static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
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{
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u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
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int ret;
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feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
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nand_select_target(chip, 0);
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ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
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feature);
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nand_deselect_target(chip);
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if (ret)
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pr_err("%s all blocks failed\n", __func__);
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return ret;
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}
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static void macronix_nand_block_protection_support(struct nand_chip *chip)
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{
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u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
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int ret;
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bitmap_set(chip->parameters.get_feature_list,
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ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
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feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
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nand_select_target(chip, 0);
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ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
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feature);
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nand_deselect_target(chip);
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if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
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if (ret)
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pr_err("Block protection check failed\n");
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bitmap_clear(chip->parameters.get_feature_list,
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ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
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return;
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}
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bitmap_set(chip->parameters.set_feature_list,
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ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
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chip->ops.lock_area = mxic_nand_lock;
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chip->ops.unlock_area = mxic_nand_unlock;
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}
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static int nand_power_down_op(struct nand_chip *chip)
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{
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int ret;
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if (nand_has_exec_op(chip)) {
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struct nand_op_instr instrs[] = {
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NAND_OP_CMD(MXIC_CMD_POWER_DOWN, 0),
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};
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struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
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ret = nand_exec_op(chip, &op);
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if (ret)
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return ret;
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} else {
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chip->legacy.cmdfunc(chip, MXIC_CMD_POWER_DOWN, -1, -1);
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}
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return 0;
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}
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static int mxic_nand_suspend(struct nand_chip *chip)
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{
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int ret;
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nand_select_target(chip, 0);
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ret = nand_power_down_op(chip);
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if (ret < 0)
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pr_err("Suspending MXIC NAND chip failed (%d)\n", ret);
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nand_deselect_target(chip);
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return ret;
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}
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static void mxic_nand_resume(struct nand_chip *chip)
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{
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/*
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* Toggle #CS pin to resume NAND device and don't care
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* of the others CLE, #WE, #RE pins status.
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* A NAND controller ensure it is able to assert/de-assert #CS
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* by sending any byte over the NAND bus.
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* i.e.,
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* NAND power down command or reset command w/o R/B# status checking.
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*/
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nand_select_target(chip, 0);
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nand_power_down_op(chip);
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/* The minimum of a recovery time tRDP is 35 us */
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usleep_range(35, 100);
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nand_deselect_target(chip);
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}
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static void macronix_nand_deep_power_down_support(struct nand_chip *chip)
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{
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int i;
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static const char * const deep_power_down_dev[] = {
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"MX30UF1G28AD",
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"MX30UF2G28AD",
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"MX30UF4G28AD",
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};
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i = match_string(deep_power_down_dev, ARRAY_SIZE(deep_power_down_dev),
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chip->parameters.model);
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if (i < 0)
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return;
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chip->ops.suspend = mxic_nand_suspend;
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chip->ops.resume = mxic_nand_resume;
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}
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static int macronix_nand_init(struct nand_chip *chip)
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{
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if (nand_is_slc(chip))
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chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
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macronix_nand_fix_broken_get_timings(chip);
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macronix_nand_onfi_init(chip);
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macronix_nand_block_protection_support(chip);
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macronix_nand_deep_power_down_support(chip);
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return 0;
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}
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const struct nand_manufacturer_ops macronix_nand_manuf_ops = {
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.init = macronix_nand_init,
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};
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