303 lines
7.8 KiB
C
303 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2017 Free Electrons
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* Copyright (C) 2017 NextThing Co
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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*/
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#include "internals.h"
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/* Bit for detecting BENAND */
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#define TOSHIBA_NAND_ID4_IS_BENAND BIT(7)
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/* Recommended to rewrite for BENAND */
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#define TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED BIT(3)
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/* ECC Status Read Command for BENAND */
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#define TOSHIBA_NAND_CMD_ECC_STATUS_READ 0x7A
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/* ECC Status Mask for BENAND */
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#define TOSHIBA_NAND_ECC_STATUS_MASK 0x0F
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/* Uncorrectable Error for BENAND */
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#define TOSHIBA_NAND_ECC_STATUS_UNCORR 0x0F
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/* Max ECC Steps for BENAND */
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#define TOSHIBA_NAND_MAX_ECC_STEPS 8
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static int toshiba_nand_benand_read_eccstatus_op(struct nand_chip *chip,
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u8 *buf)
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{
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u8 *ecc_status = buf;
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if (nand_has_exec_op(chip)) {
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const struct nand_sdr_timings *sdr =
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nand_get_sdr_timings(nand_get_interface_config(chip));
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struct nand_op_instr instrs[] = {
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NAND_OP_CMD(TOSHIBA_NAND_CMD_ECC_STATUS_READ,
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PSEC_TO_NSEC(sdr->tADL_min)),
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NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0),
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};
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struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
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return nand_exec_op(chip, &op);
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}
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return -ENOTSUPP;
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}
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static int toshiba_nand_benand_eccstatus(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret;
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unsigned int max_bitflips = 0;
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u8 status, ecc_status[TOSHIBA_NAND_MAX_ECC_STEPS];
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/* Check Status */
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ret = toshiba_nand_benand_read_eccstatus_op(chip, ecc_status);
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if (!ret) {
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unsigned int i, bitflips = 0;
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for (i = 0; i < chip->ecc.steps; i++) {
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bitflips = ecc_status[i] & TOSHIBA_NAND_ECC_STATUS_MASK;
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if (bitflips == TOSHIBA_NAND_ECC_STATUS_UNCORR) {
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mtd->ecc_stats.failed++;
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} else {
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mtd->ecc_stats.corrected += bitflips;
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max_bitflips = max(max_bitflips, bitflips);
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}
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}
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return max_bitflips;
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}
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/*
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* Fallback to regular status check if
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* toshiba_nand_benand_read_eccstatus_op() failed.
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*/
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ret = nand_status_op(chip, &status);
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if (ret)
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return ret;
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if (status & NAND_STATUS_FAIL) {
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/* uncorrected */
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mtd->ecc_stats.failed++;
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} else if (status & TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED) {
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/* corrected */
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max_bitflips = mtd->bitflip_threshold;
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mtd->ecc_stats.corrected += max_bitflips;
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}
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return max_bitflips;
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}
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static int
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toshiba_nand_read_page_benand(struct nand_chip *chip, uint8_t *buf,
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int oob_required, int page)
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{
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int ret;
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ret = nand_read_page_raw(chip, buf, oob_required, page);
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if (ret)
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return ret;
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return toshiba_nand_benand_eccstatus(chip);
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}
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static int
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toshiba_nand_read_subpage_benand(struct nand_chip *chip, uint32_t data_offs,
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uint32_t readlen, uint8_t *bufpoi, int page)
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{
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int ret;
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ret = nand_read_page_op(chip, page, data_offs,
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bufpoi + data_offs, readlen);
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if (ret)
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return ret;
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return toshiba_nand_benand_eccstatus(chip);
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}
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static void toshiba_nand_benand_init(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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/*
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* On BENAND, the entire OOB region can be used by the MTD user.
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* The calculated ECC bytes are stored into other isolated
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* area which is not accessible to users.
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* This is why chip->ecc.bytes = 0.
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*/
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chip->ecc.bytes = 0;
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chip->ecc.size = 512;
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chip->ecc.strength = 8;
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chip->ecc.read_page = toshiba_nand_read_page_benand;
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chip->ecc.read_subpage = toshiba_nand_read_subpage_benand;
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chip->ecc.write_page = nand_write_page_raw;
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chip->ecc.read_page_raw = nand_read_page_raw_notsupp;
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chip->ecc.write_page_raw = nand_write_page_raw_notsupp;
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chip->options |= NAND_SUBPAGE_READ;
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mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
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}
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static void toshiba_nand_decode_id(struct nand_chip *chip)
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{
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struct nand_device *base = &chip->base;
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struct nand_ecc_props requirements = {};
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct nand_memory_organization *memorg;
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memorg = nanddev_get_memorg(&chip->base);
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nand_decode_ext_id(chip);
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/*
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* Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
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* 512B page. For Toshiba SLC, we decode the 5th/6th byte as
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* follows:
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* - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
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* 110b -> 24nm
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* - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
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*/
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if (chip->id.len >= 6 && nand_is_slc(chip) &&
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(chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
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!(chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND) /* !BENAND */) {
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memorg->oobsize = 32 * memorg->pagesize >> 9;
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mtd->oobsize = memorg->oobsize;
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}
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/*
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* Extract ECC requirements from 6th id byte.
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* For Toshiba SLC, ecc requrements are as follows:
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* - 43nm: 1 bit ECC for each 512Byte is required.
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* - 32nm: 4 bit ECC for each 512Byte is required.
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* - 24nm: 8 bit ECC for each 512Byte is required.
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*/
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if (chip->id.len >= 6 && nand_is_slc(chip)) {
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requirements.step_size = 512;
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switch (chip->id.data[5] & 0x7) {
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case 0x4:
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requirements.strength = 1;
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break;
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case 0x5:
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requirements.strength = 4;
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break;
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case 0x6:
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requirements.strength = 8;
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break;
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default:
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WARN(1, "Could not get ECC info");
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requirements.step_size = 0;
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break;
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}
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}
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nanddev_set_ecc_requirements(base, &requirements);
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}
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static int
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tc58teg5dclta00_choose_interface_config(struct nand_chip *chip,
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struct nand_interface_config *iface)
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{
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onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 5);
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return nand_choose_best_sdr_timings(chip, iface, NULL);
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}
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static int
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tc58nvg0s3e_choose_interface_config(struct nand_chip *chip,
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struct nand_interface_config *iface)
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{
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onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 2);
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return nand_choose_best_sdr_timings(chip, iface, NULL);
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}
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static int
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th58nvg2s3hbai4_choose_interface_config(struct nand_chip *chip,
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struct nand_interface_config *iface)
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{
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struct nand_sdr_timings *sdr = &iface->timings.sdr;
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/* Start with timings from the closest timing mode, mode 4. */
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onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
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/* Patch timings that differ from mode 4. */
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sdr->tALS_min = 12000;
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sdr->tCHZ_max = 20000;
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sdr->tCLS_min = 12000;
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sdr->tCOH_min = 0;
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sdr->tDS_min = 12000;
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sdr->tRHOH_min = 25000;
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sdr->tRHW_min = 30000;
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sdr->tRHZ_max = 60000;
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sdr->tWHR_min = 60000;
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/* Patch timings not part of onfi timing mode. */
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sdr->tPROG_max = 700000000;
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sdr->tBERS_max = 5000000000;
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return nand_choose_best_sdr_timings(chip, iface, sdr);
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}
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static int tc58teg5dclta00_init(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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chip->ops.choose_interface_config =
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&tc58teg5dclta00_choose_interface_config;
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chip->options |= NAND_NEED_SCRAMBLING;
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mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme);
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return 0;
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}
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static int tc58nvg0s3e_init(struct nand_chip *chip)
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{
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chip->ops.choose_interface_config =
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&tc58nvg0s3e_choose_interface_config;
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return 0;
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}
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static int th58nvg2s3hbai4_init(struct nand_chip *chip)
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{
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chip->ops.choose_interface_config =
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&th58nvg2s3hbai4_choose_interface_config;
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return 0;
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}
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static int toshiba_nand_init(struct nand_chip *chip)
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{
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if (nand_is_slc(chip))
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chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
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/* Check that chip is BENAND and ECC mode is on-die */
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if (nand_is_slc(chip) &&
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chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE &&
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chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND)
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toshiba_nand_benand_init(chip);
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if (!strcmp("TC58TEG5DCLTA00", chip->parameters.model))
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tc58teg5dclta00_init(chip);
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if (!strncmp("TC58NVG0S3E", chip->parameters.model,
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sizeof("TC58NVG0S3E") - 1))
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tc58nvg0s3e_init(chip);
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if ((!strncmp("TH58NVG2S3HBAI4", chip->parameters.model,
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sizeof("TH58NVG2S3HBAI4") - 1)) ||
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(!strncmp("TH58NVG3S0HBAI4", chip->parameters.model,
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sizeof("TH58NVG3S0HBAI4") - 1)))
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th58nvg2s3hbai4_init(chip);
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return 0;
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}
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const struct nand_manufacturer_ops toshiba_nand_manuf_ops = {
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.detect = toshiba_nand_decode_id,
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.init = toshiba_nand_init,
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};
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