78 lines
2.6 KiB
C
78 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*******************************************************************************
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*
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* CTU CAN FD IP Core
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*
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Project advisors:
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* Jiri Novak <jnovak@fel.cvut.cz>
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* Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Department of Measurement (http://meas.fel.cvut.cz/)
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* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
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* Czech Technical University (http://www.cvut.cz/)
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******************************************************************************/
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/* This file is autogenerated, DO NOT EDIT! */
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#ifndef __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
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#define __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
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#include <linux/bits.h>
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/* CAN_Frame_format memory map */
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enum ctu_can_fd_can_frame_format {
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CTUCANFD_FRAME_FORMAT_W = 0x0,
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CTUCANFD_IDENTIFIER_W = 0x4,
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CTUCANFD_TIMESTAMP_L_W = 0x8,
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CTUCANFD_TIMESTAMP_U_W = 0xc,
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CTUCANFD_DATA_1_4_W = 0x10,
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CTUCANFD_DATA_5_8_W = 0x14,
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CTUCANFD_DATA_61_64_W = 0x4c,
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};
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/* CAN_FD_Frame_format memory region */
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/* FRAME_FORMAT_W registers */
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#define REG_FRAME_FORMAT_W_DLC GENMASK(3, 0)
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#define REG_FRAME_FORMAT_W_RTR BIT(5)
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#define REG_FRAME_FORMAT_W_IDE BIT(6)
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#define REG_FRAME_FORMAT_W_FDF BIT(7)
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#define REG_FRAME_FORMAT_W_BRS BIT(9)
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#define REG_FRAME_FORMAT_W_ESI_RSV BIT(10)
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#define REG_FRAME_FORMAT_W_RWCNT GENMASK(15, 11)
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/* IDENTIFIER_W registers */
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#define REG_IDENTIFIER_W_IDENTIFIER_EXT GENMASK(17, 0)
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#define REG_IDENTIFIER_W_IDENTIFIER_BASE GENMASK(28, 18)
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/* TIMESTAMP_L_W registers */
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#define REG_TIMESTAMP_L_W_TIME_STAMP_L_W GENMASK(31, 0)
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/* TIMESTAMP_U_W registers */
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#define REG_TIMESTAMP_U_W_TIMESTAMP_U_W GENMASK(31, 0)
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/* DATA_1_4_W registers */
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#define REG_DATA_1_4_W_DATA_1 GENMASK(7, 0)
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#define REG_DATA_1_4_W_DATA_2 GENMASK(15, 8)
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#define REG_DATA_1_4_W_DATA_3 GENMASK(23, 16)
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#define REG_DATA_1_4_W_DATA_4 GENMASK(31, 24)
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/* DATA_5_8_W registers */
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#define REG_DATA_5_8_W_DATA_5 GENMASK(7, 0)
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#define REG_DATA_5_8_W_DATA_6 GENMASK(15, 8)
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#define REG_DATA_5_8_W_DATA_7 GENMASK(23, 16)
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#define REG_DATA_5_8_W_DATA_8 GENMASK(31, 24)
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/* DATA_61_64_W registers */
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#define REG_DATA_61_64_W_DATA_61 GENMASK(7, 0)
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#define REG_DATA_61_64_W_DATA_62 GENMASK(15, 8)
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#define REG_DATA_61_64_W_DATA_63 GENMASK(23, 16)
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#define REG_DATA_61_64_W_DATA_64 GENMASK(31, 24)
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#endif
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