449 lines
11 KiB
C
449 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 Intel Corporation */
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#include <linux/delay.h>
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#include "igc_hw.h"
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#include "igc_i225.h"
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#include "igc_mac.h"
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#include "igc_base.h"
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#include "igc.h"
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/**
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* igc_reset_hw_base - Reset hardware
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* @hw: pointer to the HW structure
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*
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* This resets the hardware into a known state. This is a
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* function pointer entry point called by the api module.
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*/
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static s32 igc_reset_hw_base(struct igc_hw *hw)
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{
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s32 ret_val;
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u32 ctrl;
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/* Prevent the PCI-E bus from sticking if there is no TLP connection
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* on the last TLP read/write transaction when MAC is reset.
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*/
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ret_val = igc_disable_pcie_master(hw);
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if (ret_val)
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hw_dbg("PCI-E Master disable polling has failed\n");
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hw_dbg("Masking off all interrupts\n");
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wr32(IGC_IMC, 0xffffffff);
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wr32(IGC_RCTL, 0);
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wr32(IGC_TCTL, IGC_TCTL_PSP);
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wrfl();
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usleep_range(10000, 20000);
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ctrl = rd32(IGC_CTRL);
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hw_dbg("Issuing a global reset to MAC\n");
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wr32(IGC_CTRL, ctrl | IGC_CTRL_RST);
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ret_val = igc_get_auto_rd_done(hw);
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if (ret_val) {
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/* When auto config read does not complete, do not
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* return with an error. This can happen in situations
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* where there is no eeprom and prevents getting link.
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*/
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hw_dbg("Auto Read Done did not complete\n");
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}
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/* Clear any pending interrupt events. */
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wr32(IGC_IMC, 0xffffffff);
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rd32(IGC_ICR);
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return ret_val;
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}
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/**
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* igc_init_nvm_params_base - Init NVM func ptrs.
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* @hw: pointer to the HW structure
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*/
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static s32 igc_init_nvm_params_base(struct igc_hw *hw)
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{
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struct igc_nvm_info *nvm = &hw->nvm;
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u32 eecd = rd32(IGC_EECD);
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u16 size;
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size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >>
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IGC_EECD_SIZE_EX_SHIFT);
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/* Added to a constant, "size" becomes the left-shift value
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* for setting word_size.
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*/
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size += NVM_WORD_SIZE_BASE_SHIFT;
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/* Just in case size is out of range, cap it to the largest
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* EEPROM size supported
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*/
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if (size > 15)
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size = 15;
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nvm->type = igc_nvm_eeprom_spi;
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nvm->word_size = BIT(size);
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nvm->opcode_bits = 8;
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nvm->delay_usec = 1;
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nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;
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nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?
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16 : 8;
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if (nvm->word_size == BIT(15))
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nvm->page_size = 128;
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return 0;
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}
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/**
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* igc_setup_copper_link_base - Configure copper link settings
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* @hw: pointer to the HW structure
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*
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* Configures the link for auto-neg or forced speed and duplex. Then we check
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* for link, once link is established calls to configure collision distance
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* and flow control are called.
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*/
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static s32 igc_setup_copper_link_base(struct igc_hw *hw)
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{
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s32 ret_val = 0;
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u32 ctrl;
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ctrl = rd32(IGC_CTRL);
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ctrl |= IGC_CTRL_SLU;
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ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
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wr32(IGC_CTRL, ctrl);
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ret_val = igc_setup_copper_link(hw);
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return ret_val;
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}
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/**
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* igc_init_mac_params_base - Init MAC func ptrs.
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* @hw: pointer to the HW structure
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*/
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static s32 igc_init_mac_params_base(struct igc_hw *hw)
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{
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struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base;
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struct igc_mac_info *mac = &hw->mac;
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/* Set mta register count */
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mac->mta_reg_count = 128;
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mac->rar_entry_count = IGC_RAR_ENTRIES;
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/* reset */
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mac->ops.reset_hw = igc_reset_hw_base;
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mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;
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mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;
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/* Allow a single clear of the SW semaphore on I225 */
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if (mac->type == igc_i225)
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dev_spec->clear_semaphore_once = true;
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/* physical interface link setup */
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mac->ops.setup_physical_interface = igc_setup_copper_link_base;
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return 0;
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}
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/**
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* igc_init_phy_params_base - Init PHY func ptrs.
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* @hw: pointer to the HW structure
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*/
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static s32 igc_init_phy_params_base(struct igc_hw *hw)
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{
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struct igc_phy_info *phy = &hw->phy;
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s32 ret_val = 0;
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;
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phy->reset_delay_us = 100;
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/* set lan id */
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hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >>
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IGC_STATUS_FUNC_SHIFT;
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/* Make sure the PHY is in a good state. Several people have reported
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* firmware leaving the PHY's page select register set to something
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* other than the default of zero, which causes the PHY ID read to
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* access something other than the intended register.
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*/
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ret_val = hw->phy.ops.reset(hw);
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if (ret_val) {
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hw_dbg("Error resetting the PHY\n");
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goto out;
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}
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ret_val = igc_get_phy_id(hw);
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if (ret_val)
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return ret_val;
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igc_check_for_copper_link(hw);
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out:
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return ret_val;
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}
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static s32 igc_get_invariants_base(struct igc_hw *hw)
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{
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struct igc_mac_info *mac = &hw->mac;
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s32 ret_val = 0;
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switch (hw->device_id) {
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case IGC_DEV_ID_I225_LM:
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case IGC_DEV_ID_I225_V:
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case IGC_DEV_ID_I225_I:
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case IGC_DEV_ID_I220_V:
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case IGC_DEV_ID_I225_K:
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case IGC_DEV_ID_I225_K2:
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case IGC_DEV_ID_I226_K:
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case IGC_DEV_ID_I225_LMVP:
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case IGC_DEV_ID_I226_LMVP:
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case IGC_DEV_ID_I225_IT:
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case IGC_DEV_ID_I226_LM:
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case IGC_DEV_ID_I226_V:
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case IGC_DEV_ID_I226_IT:
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case IGC_DEV_ID_I221_V:
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case IGC_DEV_ID_I226_BLANK_NVM:
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case IGC_DEV_ID_I225_BLANK_NVM:
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mac->type = igc_i225;
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break;
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default:
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return -IGC_ERR_MAC_INIT;
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}
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hw->phy.media_type = igc_media_type_copper;
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/* mac initialization and operations */
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ret_val = igc_init_mac_params_base(hw);
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if (ret_val)
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goto out;
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/* NVM initialization */
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ret_val = igc_init_nvm_params_base(hw);
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switch (hw->mac.type) {
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case igc_i225:
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ret_val = igc_init_nvm_params_i225(hw);
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break;
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default:
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break;
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}
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/* setup PHY parameters */
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ret_val = igc_init_phy_params_base(hw);
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if (ret_val)
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goto out;
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out:
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return ret_val;
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}
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/**
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* igc_acquire_phy_base - Acquire rights to access PHY
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* @hw: pointer to the HW structure
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*
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* Acquire access rights to the correct PHY. This is a
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* function pointer entry point called by the api module.
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*/
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static s32 igc_acquire_phy_base(struct igc_hw *hw)
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{
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u16 mask = IGC_SWFW_PHY0_SM;
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return hw->mac.ops.acquire_swfw_sync(hw, mask);
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}
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/**
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* igc_release_phy_base - Release rights to access PHY
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* @hw: pointer to the HW structure
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*
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* A wrapper to release access rights to the correct PHY. This is a
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* function pointer entry point called by the api module.
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*/
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static void igc_release_phy_base(struct igc_hw *hw)
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{
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u16 mask = IGC_SWFW_PHY0_SM;
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hw->mac.ops.release_swfw_sync(hw, mask);
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}
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/**
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* igc_init_hw_base - Initialize hardware
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* @hw: pointer to the HW structure
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*
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* This inits the hardware readying it for operation.
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*/
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static s32 igc_init_hw_base(struct igc_hw *hw)
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{
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struct igc_mac_info *mac = &hw->mac;
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u16 i, rar_count = mac->rar_entry_count;
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s32 ret_val = 0;
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/* Setup the receive address */
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igc_init_rx_addrs(hw, rar_count);
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/* Zero out the Multicast HASH table */
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hw_dbg("Zeroing the MTA\n");
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for (i = 0; i < mac->mta_reg_count; i++)
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array_wr32(IGC_MTA, i, 0);
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/* Zero out the Unicast HASH table */
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hw_dbg("Zeroing the UTA\n");
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for (i = 0; i < mac->uta_reg_count; i++)
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array_wr32(IGC_UTA, i, 0);
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/* Setup link and flow control */
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ret_val = igc_setup_link(hw);
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/* Clear all of the statistics registers (clear on read). It is
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* important that we do this after we have tried to establish link
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* because the symbol error count will increment wildly if there
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* is no link.
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*/
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igc_clear_hw_cntrs_base(hw);
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return ret_val;
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}
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/**
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* igc_power_down_phy_copper_base - Remove link during PHY power down
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* @hw: pointer to the HW structure
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*
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* In the case of a PHY power down to save power, or to turn off link during a
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* driver unload, or wake on lan is not enabled, remove the link.
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*/
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void igc_power_down_phy_copper_base(struct igc_hw *hw)
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{
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/* If the management interface is not enabled, then power down */
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if (!(igc_enable_mng_pass_thru(hw) || igc_check_reset_block(hw)))
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igc_power_down_phy_copper(hw);
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}
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/**
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* igc_rx_fifo_flush_base - Clean rx fifo after Rx enable
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* @hw: pointer to the HW structure
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*
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* After Rx enable, if manageability is enabled then there is likely some
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* bad data at the start of the fifo and possibly in the DMA fifo. This
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* function clears the fifos and flushes any packets that came in as rx was
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* being enabled.
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*/
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void igc_rx_fifo_flush_base(struct igc_hw *hw)
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{
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u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
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int i, ms_wait;
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/* disable IPv6 options as per hardware errata */
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rfctl = rd32(IGC_RFCTL);
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rfctl |= IGC_RFCTL_IPV6_EX_DIS;
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wr32(IGC_RFCTL, rfctl);
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if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN))
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return;
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/* Disable all Rx queues */
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for (i = 0; i < 4; i++) {
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rxdctl[i] = rd32(IGC_RXDCTL(i));
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wr32(IGC_RXDCTL(i),
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rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
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}
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/* Poll all queues to verify they have shut down */
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for (ms_wait = 0; ms_wait < 10; ms_wait++) {
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usleep_range(1000, 2000);
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rx_enabled = 0;
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for (i = 0; i < 4; i++)
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rx_enabled |= rd32(IGC_RXDCTL(i));
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if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
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break;
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}
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if (ms_wait == 10)
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hw_dbg("Queue disable timed out after 10ms\n");
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/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
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* incoming packets are rejected. Set enable and wait 2ms so that
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* any packet that was coming in as RCTL.EN was set is flushed
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*/
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wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);
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rlpml = rd32(IGC_RLPML);
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wr32(IGC_RLPML, 0);
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rctl = rd32(IGC_RCTL);
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temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
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temp_rctl |= IGC_RCTL_LPE;
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wr32(IGC_RCTL, temp_rctl);
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wr32(IGC_RCTL, temp_rctl | IGC_RCTL_EN);
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wrfl();
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usleep_range(2000, 3000);
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/* Enable Rx queues that were previously enabled and restore our
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* previous state
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*/
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for (i = 0; i < 4; i++)
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wr32(IGC_RXDCTL(i), rxdctl[i]);
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wr32(IGC_RCTL, rctl);
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wrfl();
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wr32(IGC_RLPML, rlpml);
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wr32(IGC_RFCTL, rfctl);
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/* Flush receive errors generated by workaround */
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rd32(IGC_ROC);
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rd32(IGC_RNBC);
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rd32(IGC_MPC);
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}
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bool igc_is_device_id_i225(struct igc_hw *hw)
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{
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switch (hw->device_id) {
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case IGC_DEV_ID_I225_LM:
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case IGC_DEV_ID_I225_V:
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case IGC_DEV_ID_I225_I:
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case IGC_DEV_ID_I225_K:
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case IGC_DEV_ID_I225_K2:
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case IGC_DEV_ID_I225_LMVP:
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case IGC_DEV_ID_I225_IT:
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return true;
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default:
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return false;
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}
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}
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bool igc_is_device_id_i226(struct igc_hw *hw)
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{
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switch (hw->device_id) {
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case IGC_DEV_ID_I226_LM:
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case IGC_DEV_ID_I226_V:
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case IGC_DEV_ID_I226_K:
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case IGC_DEV_ID_I226_IT:
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return true;
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default:
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return false;
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}
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}
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static struct igc_mac_operations igc_mac_ops_base = {
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.init_hw = igc_init_hw_base,
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.check_for_link = igc_check_for_copper_link,
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.rar_set = igc_rar_set,
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.read_mac_addr = igc_read_mac_addr,
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.get_speed_and_duplex = igc_get_speed_and_duplex_copper,
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};
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static const struct igc_phy_operations igc_phy_ops_base = {
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.acquire = igc_acquire_phy_base,
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.release = igc_release_phy_base,
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.reset = igc_phy_hw_reset,
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.read_reg = igc_read_phy_reg_gpy,
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.write_reg = igc_write_phy_reg_gpy,
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};
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const struct igc_info igc_base_info = {
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.get_invariants = igc_get_invariants_base,
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.mac_ops = &igc_mac_ops_base,
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.phy_ops = &igc_phy_ops_base,
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};
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