716 lines
18 KiB
C
716 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Marvell CN10K RPM driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#include "cgx.h"
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#include "lmac_common.h"
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static struct mac_ops rpm_mac_ops = {
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.name = "rpm",
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.csr_offset = 0x4e00,
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.lmac_offset = 20,
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.int_register = RPMX_CMRX_SW_INT,
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.int_set_reg = RPMX_CMRX_SW_INT_ENA_W1S,
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.irq_offset = 1,
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.int_ena_bit = BIT_ULL(0),
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.lmac_fwi = RPM_LMAC_FWI,
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.non_contiguous_serdes_lane = true,
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.rx_stats_cnt = 43,
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.tx_stats_cnt = 34,
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.dmac_filter_count = 32,
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.get_nr_lmacs = rpm_get_nr_lmacs,
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.get_lmac_type = rpm_get_lmac_type,
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.lmac_fifo_len = rpm_get_lmac_fifo_len,
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.mac_lmac_intl_lbk = rpm_lmac_internal_loopback,
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.mac_get_rx_stats = rpm_get_rx_stats,
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.mac_get_tx_stats = rpm_get_tx_stats,
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.get_fec_stats = rpm_get_fec_stats,
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.mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding,
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.mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status,
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.mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm,
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.mac_pause_frm_config = rpm_lmac_pause_frm_config,
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.mac_enadis_ptp_config = rpm_lmac_ptp_config,
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.mac_rx_tx_enable = rpm_lmac_rx_tx_enable,
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.mac_tx_enable = rpm_lmac_tx_enable,
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.pfc_config = rpm_lmac_pfc_config,
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.mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg,
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};
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static struct mac_ops rpm2_mac_ops = {
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.name = "rpm",
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.csr_offset = RPM2_CSR_OFFSET,
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.lmac_offset = 20,
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.int_register = RPM2_CMRX_SW_INT,
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.int_set_reg = RPM2_CMRX_SW_INT_ENA_W1S,
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.irq_offset = 1,
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.int_ena_bit = BIT_ULL(0),
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.lmac_fwi = RPM_LMAC_FWI,
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.non_contiguous_serdes_lane = true,
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.rx_stats_cnt = 43,
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.tx_stats_cnt = 34,
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.dmac_filter_count = 64,
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.get_nr_lmacs = rpm2_get_nr_lmacs,
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.get_lmac_type = rpm_get_lmac_type,
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.lmac_fifo_len = rpm2_get_lmac_fifo_len,
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.mac_lmac_intl_lbk = rpm_lmac_internal_loopback,
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.mac_get_rx_stats = rpm_get_rx_stats,
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.mac_get_tx_stats = rpm_get_tx_stats,
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.get_fec_stats = rpm_get_fec_stats,
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.mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding,
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.mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status,
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.mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm,
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.mac_pause_frm_config = rpm_lmac_pause_frm_config,
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.mac_enadis_ptp_config = rpm_lmac_ptp_config,
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.mac_rx_tx_enable = rpm_lmac_rx_tx_enable,
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.mac_tx_enable = rpm_lmac_tx_enable,
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.pfc_config = rpm_lmac_pfc_config,
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.mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg,
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};
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bool is_dev_rpm2(void *rpmd)
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{
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rpm_t *rpm = rpmd;
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return (rpm->pdev->device == PCI_DEVID_CN10KB_RPM);
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}
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struct mac_ops *rpm_get_mac_ops(rpm_t *rpm)
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{
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if (is_dev_rpm2(rpm))
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return &rpm2_mac_ops;
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else
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return &rpm_mac_ops;
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}
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static void rpm_write(rpm_t *rpm, u64 lmac, u64 offset, u64 val)
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{
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cgx_write(rpm, lmac, offset, val);
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}
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static u64 rpm_read(rpm_t *rpm, u64 lmac, u64 offset)
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{
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return cgx_read(rpm, lmac, offset);
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}
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/* Read HW major version to determine RPM
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* MAC type 100/USX
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*/
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static bool is_mac_rpmusx(void *rpmd)
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{
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rpm_t *rpm = rpmd;
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return rpm_read(rpm, 0, RPMX_CONST1) & 0x700ULL;
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}
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int rpm_get_nr_lmacs(void *rpmd)
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{
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rpm_t *rpm = rpmd;
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return hweight8(rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS) & 0xFULL);
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}
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int rpm2_get_nr_lmacs(void *rpmd)
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{
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rpm_t *rpm = rpmd;
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return hweight8(rpm_read(rpm, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL);
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}
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int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable)
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{
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rpm_t *rpm = rpmd;
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u64 cfg, last;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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last = cfg;
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if (enable)
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cfg |= RPM_TX_EN;
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else
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cfg &= ~(RPM_TX_EN);
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if (cfg != last)
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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return !!(last & RPM_TX_EN);
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}
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int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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if (enable)
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cfg |= RPM_RX_EN | RPM_TX_EN;
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else
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cfg &= ~(RPM_RX_EN | RPM_TX_EN);
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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return 0;
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}
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void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable)
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{
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rpm_t *rpm = rpmd;
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struct lmac *lmac;
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u64 cfg;
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if (!rpm)
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return;
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lmac = lmac_pdata(lmac_id, rpm);
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if (!lmac)
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return;
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/* Pause frames are not enabled just return */
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if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max))
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return;
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if (enable) {
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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} else {
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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}
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}
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int rpm_lmac_get_pause_frm_status(void *rpmd, int lmac_id,
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u8 *tx_pause, u8 *rx_pause)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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if (!(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE)) {
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*rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE);
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*tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE);
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}
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return 0;
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}
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static void rpm_cfg_pfc_quanta_thresh(rpm_t *rpm, int lmac_id,
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unsigned long pfc_en,
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bool enable)
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{
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u64 quanta_offset = 0, quanta_thresh = 0, cfg;
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int i, shift;
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/* Set pause time and interval */
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for_each_set_bit(i, &pfc_en, 16) {
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switch (i) {
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case 0:
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case 1:
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quanta_offset = RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL01_QUANTA_THRESH;
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break;
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case 2:
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case 3:
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quanta_offset = RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL23_QUANTA_THRESH;
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break;
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case 4:
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case 5:
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quanta_offset = RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL45_QUANTA_THRESH;
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break;
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case 6:
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case 7:
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quanta_offset = RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL67_QUANTA_THRESH;
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break;
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case 8:
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case 9:
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quanta_offset = RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL89_QUANTA_THRESH;
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break;
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case 10:
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case 11:
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quanta_offset = RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH;
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break;
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case 12:
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case 13:
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quanta_offset = RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH;
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break;
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case 14:
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case 15:
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quanta_offset = RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA;
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quanta_thresh = RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH;
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break;
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}
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if (!quanta_offset || !quanta_thresh)
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continue;
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shift = (i % 2) ? 1 : 0;
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cfg = rpm_read(rpm, lmac_id, quanta_offset);
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if (enable) {
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cfg |= ((u64)RPM_DEFAULT_PAUSE_TIME << shift * 16);
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} else {
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if (!shift)
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cfg &= ~GENMASK_ULL(15, 0);
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else
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cfg &= ~GENMASK_ULL(31, 16);
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}
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rpm_write(rpm, lmac_id, quanta_offset, cfg);
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cfg = rpm_read(rpm, lmac_id, quanta_thresh);
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if (enable) {
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cfg |= ((u64)(RPM_DEFAULT_PAUSE_TIME / 2) << shift * 16);
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} else {
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if (!shift)
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cfg &= ~GENMASK_ULL(15, 0);
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else
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cfg &= ~GENMASK_ULL(31, 16);
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}
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rpm_write(rpm, lmac_id, quanta_thresh, cfg);
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}
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}
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static void rpm2_lmac_cfg_bp(rpm_t *rpm, int lmac_id, u8 tx_pause, u8 rx_pause)
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{
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u64 cfg;
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cfg = rpm_read(rpm, lmac_id, RPM2_CMR_RX_OVR_BP);
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if (tx_pause) {
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/* Configure CL0 Pause Quanta & threshold
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* for 802.3X frames
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*/
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rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true);
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cfg &= ~RPM2_CMR_RX_OVR_BP_EN;
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} else {
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/* Disable all Pause Quanta & threshold values */
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rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false);
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cfg |= RPM2_CMR_RX_OVR_BP_EN;
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cfg &= ~RPM2_CMR_RX_OVR_BP_BP;
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}
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rpm_write(rpm, lmac_id, RPM2_CMR_RX_OVR_BP, cfg);
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}
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static void rpm_lmac_cfg_bp(rpm_t *rpm, int lmac_id, u8 tx_pause, u8 rx_pause)
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{
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u64 cfg;
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cfg = rpm_read(rpm, 0, RPMX_CMR_RX_OVR_BP);
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if (tx_pause) {
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/* Configure CL0 Pause Quanta & threshold for
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* 802.3X frames
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*/
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rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true);
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cfg &= ~RPMX_CMR_RX_OVR_BP_EN(lmac_id);
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} else {
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/* Disable all Pause Quanta & threshold values */
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rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false);
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cfg |= RPMX_CMR_RX_OVR_BP_EN(lmac_id);
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cfg &= ~RPMX_CMR_RX_OVR_BP_BP(lmac_id);
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}
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rpm_write(rpm, 0, RPMX_CMR_RX_OVR_BP, cfg);
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}
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int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,
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u8 rx_pause)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
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cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
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cfg |= tx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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if (is_dev_rpm2(rpm))
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rpm2_lmac_cfg_bp(rpm, lmac_id, tx_pause, rx_pause);
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else
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rpm_lmac_cfg_bp(rpm, lmac_id, tx_pause, rx_pause);
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return 0;
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}
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void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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/* ALL pause frames received are completely ignored */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Disable forward pause to TX block */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Disable pause frames transmission */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Enable channel mask for all LMACS */
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if (is_dev_rpm2(rpm))
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rpm_write(rpm, lmac_id, RPM2_CMR_CHAN_MSK_OR, 0xffff);
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else
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rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL);
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/* Disable all PFC classes */
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cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL);
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cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg);
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rpm_write(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL, cfg);
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}
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int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat)
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{
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rpm_t *rpm = rpmd;
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u64 val_lo, val_hi;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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mutex_lock(&rpm->lock);
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/* Update idx to point per lmac Rx statistics page */
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idx += lmac_id * rpm->mac_ops->rx_stats_cnt;
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/* Read lower 32 bits of counter */
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val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX +
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(idx * 8));
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/* upon read of lower 32 bits, higher 32 bits are written
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* to RPMX_MTI_STAT_DATA_HI_CDC
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*/
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val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
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*rx_stat = (val_hi << 32 | val_lo);
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mutex_unlock(&rpm->lock);
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return 0;
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}
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int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat)
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{
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rpm_t *rpm = rpmd;
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u64 val_lo, val_hi;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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mutex_lock(&rpm->lock);
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/* Update idx to point per lmac Tx statistics page */
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idx += lmac_id * rpm->mac_ops->tx_stats_cnt;
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val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX +
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(idx * 8));
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val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
|
|
|
|
*tx_stat = (val_hi << 32 | val_lo);
|
|
|
|
mutex_unlock(&rpm->lock);
|
|
return 0;
|
|
}
|
|
|
|
u8 rpm_get_lmac_type(void *rpmd, int lmac_id)
|
|
{
|
|
rpm_t *rpm = rpmd;
|
|
u64 req = 0, resp;
|
|
int err;
|
|
|
|
req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_LINK_STS, req);
|
|
err = cgx_fwi_cmd_generic(req, &resp, rpm, 0);
|
|
if (!err)
|
|
return FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, resp);
|
|
return err;
|
|
}
|
|
|
|
u32 rpm_get_lmac_fifo_len(void *rpmd, int lmac_id)
|
|
{
|
|
rpm_t *rpm = rpmd;
|
|
u64 hi_perf_lmac;
|
|
u8 num_lmacs;
|
|
u32 fifo_len;
|
|
|
|
fifo_len = rpm->mac_ops->fifo_len;
|
|
num_lmacs = rpm->mac_ops->get_nr_lmacs(rpm);
|
|
|
|
switch (num_lmacs) {
|
|
case 1:
|
|
return fifo_len;
|
|
case 2:
|
|
return fifo_len / 2;
|
|
case 3:
|
|
/* LMAC marked as hi_perf gets half of the FIFO and rest 1/4th */
|
|
hi_perf_lmac = rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS);
|
|
hi_perf_lmac = (hi_perf_lmac >> 4) & 0x3ULL;
|
|
if (lmac_id == hi_perf_lmac)
|
|
return fifo_len / 2;
|
|
return fifo_len / 4;
|
|
case 4:
|
|
default:
|
|
return fifo_len / 4;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int rpmusx_lmac_internal_loopback(rpm_t *rpm, int lmac_id, bool enable)
|
|
{
|
|
u64 cfg;
|
|
|
|
cfg = rpm_read(rpm, lmac_id, RPM2_USX_PCSX_CONTROL1);
|
|
|
|
if (enable)
|
|
cfg |= RPM2_USX_PCS_LBK;
|
|
else
|
|
cfg &= ~RPM2_USX_PCS_LBK;
|
|
rpm_write(rpm, lmac_id, RPM2_USX_PCSX_CONTROL1, cfg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id)
|
|
{
|
|
u64 hi_perf_lmac, lmac_info;
|
|
rpm_t *rpm = rpmd;
|
|
u8 num_lmacs;
|
|
u32 fifo_len;
|
|
|
|
lmac_info = rpm_read(rpm, 0, RPM2_CMRX_RX_LMACS);
|
|
/* LMACs are divided into two groups and each group
|
|
* gets half of the FIFO
|
|
* Group0 lmac_id range {0..3}
|
|
* Group1 lmac_id range {4..7}
|
|
*/
|
|
fifo_len = rpm->mac_ops->fifo_len / 2;
|
|
|
|
if (lmac_id < 4) {
|
|
num_lmacs = hweight8(lmac_info & 0xF);
|
|
hi_perf_lmac = (lmac_info >> 8) & 0x3ULL;
|
|
} else {
|
|
num_lmacs = hweight8(lmac_info & 0xF0);
|
|
hi_perf_lmac = (lmac_info >> 10) & 0x3ULL;
|
|
hi_perf_lmac += 4;
|
|
}
|
|
|
|
switch (num_lmacs) {
|
|
case 1:
|
|
return fifo_len;
|
|
case 2:
|
|
return fifo_len / 2;
|
|
case 3:
|
|
/* LMAC marked as hi_perf gets half of the FIFO
|
|
* and rest 1/4th
|
|
*/
|
|
if (lmac_id == hi_perf_lmac)
|
|
return fifo_len / 2;
|
|
return fifo_len / 4;
|
|
case 4:
|
|
default:
|
|
return fifo_len / 4;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable)
|
|
{
|
|
rpm_t *rpm = rpmd;
|
|
u8 lmac_type;
|
|
u64 cfg;
|
|
|
|
if (!is_lmac_valid(rpm, lmac_id))
|
|
return -ENODEV;
|
|
lmac_type = rpm->mac_ops->get_lmac_type(rpm, lmac_id);
|
|
|
|
if (lmac_type == LMAC_MODE_QSGMII || lmac_type == LMAC_MODE_SGMII) {
|
|
dev_err(&rpm->pdev->dev, "loopback not supported for LPC mode\n");
|
|
return 0;
|
|
}
|
|
|
|
if (is_dev_rpm2(rpm) && is_mac_rpmusx(rpm))
|
|
return rpmusx_lmac_internal_loopback(rpm, lmac_id, enable);
|
|
|
|
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1);
|
|
|
|
if (enable)
|
|
cfg |= RPMX_MTI_PCS_LBK;
|
|
else
|
|
cfg &= ~RPMX_MTI_PCS_LBK;
|
|
rpm_write(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1, cfg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable)
|
|
{
|
|
rpm_t *rpm = rpmd;
|
|
u64 cfg;
|
|
|
|
if (!is_lmac_valid(rpm, lmac_id))
|
|
return;
|
|
|
|
cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_CFG);
|
|
if (enable) {
|
|
cfg |= RPMX_RX_TS_PREPEND;
|
|
cfg |= RPMX_TX_PTP_1S_SUPPORT;
|
|
} else {
|
|
cfg &= ~RPMX_RX_TS_PREPEND;
|
|
cfg &= ~RPMX_TX_PTP_1S_SUPPORT;
|
|
}
|
|
|
|
rpm_write(rpm, lmac_id, RPMX_CMRX_CFG, cfg);
|
|
|
|
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE);
|
|
|
|
if (enable) {
|
|
cfg |= RPMX_ONESTEP_ENABLE;
|
|
cfg &= ~RPMX_TS_BINARY_MODE;
|
|
} else {
|
|
cfg &= ~RPMX_ONESTEP_ENABLE;
|
|
}
|
|
|
|
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE, cfg);
|
|
}
|
|
|
|
int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en)
|
|
{
|
|
u64 cfg, class_en, pfc_class_mask_cfg;
|
|
rpm_t *rpm = rpmd;
|
|
|
|
if (!is_lmac_valid(rpm, lmac_id))
|
|
return -ENODEV;
|
|
|
|
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
|
|
class_en = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL);
|
|
pfc_en |= FIELD_GET(RPM_PFC_CLASS_MASK, class_en);
|
|
|
|
if (rx_pause) {
|
|
cfg &= ~(RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |
|
|
RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE |
|
|
RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD);
|
|
} else {
|
|
cfg |= (RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |
|
|
RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE |
|
|
RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD);
|
|
}
|
|
|
|
if (tx_pause) {
|
|
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, pfc_en, true);
|
|
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
|
|
class_en = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, class_en);
|
|
} else {
|
|
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xfff, false);
|
|
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
|
|
class_en = FIELD_SET(RPM_PFC_CLASS_MASK, 0, class_en);
|
|
}
|
|
|
|
if (!rx_pause && !tx_pause)
|
|
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;
|
|
else
|
|
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;
|
|
|
|
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
|
|
|
|
pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
|
|
RPMX_CMRX_PRT_CBFC_CTL;
|
|
|
|
rpm_write(rpm, lmac_id, pfc_class_mask_cfg, class_en);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, u8 *rx_pause)
|
|
{
|
|
rpm_t *rpm = rpmd;
|
|
u64 cfg;
|
|
|
|
if (!is_lmac_valid(rpm, lmac_id))
|
|
return -ENODEV;
|
|
|
|
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
|
|
if (cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE) {
|
|
*rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE);
|
|
*tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int rpm_get_fec_stats(void *rpmd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
|
|
{
|
|
u64 val_lo, val_hi;
|
|
rpm_t *rpm = rpmd;
|
|
u64 cfg;
|
|
|
|
if (!is_lmac_valid(rpm, lmac_id))
|
|
return -ENODEV;
|
|
|
|
if (rpm->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE)
|
|
return 0;
|
|
|
|
if (rpm->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
|
|
val_lo = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_VL0_CCW_LO);
|
|
val_hi = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_CW_HI);
|
|
rsp->fec_corr_blks = (val_hi << 16 | val_lo);
|
|
|
|
val_lo = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_VL0_NCCW_LO);
|
|
val_hi = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_CW_HI);
|
|
rsp->fec_uncorr_blks = (val_hi << 16 | val_lo);
|
|
|
|
/* 50G uses 2 Physical serdes lines */
|
|
if (rpm->lmac_idmap[lmac_id]->link_info.lmac_type_id ==
|
|
LMAC_MODE_50G_R) {
|
|
val_lo = rpm_read(rpm, lmac_id,
|
|
RPMX_MTI_FCFECX_VL1_CCW_LO);
|
|
val_hi = rpm_read(rpm, lmac_id,
|
|
RPMX_MTI_FCFECX_CW_HI);
|
|
rsp->fec_corr_blks += (val_hi << 16 | val_lo);
|
|
|
|
val_lo = rpm_read(rpm, lmac_id,
|
|
RPMX_MTI_FCFECX_VL1_NCCW_LO);
|
|
val_hi = rpm_read(rpm, lmac_id,
|
|
RPMX_MTI_FCFECX_CW_HI);
|
|
rsp->fec_uncorr_blks += (val_hi << 16 | val_lo);
|
|
}
|
|
} else {
|
|
/* enable RS-FEC capture */
|
|
cfg = rpm_read(rpm, 0, RPMX_MTI_STAT_STATN_CONTROL);
|
|
cfg |= RPMX_RSFEC_RX_CAPTURE | BIT(lmac_id);
|
|
rpm_write(rpm, 0, RPMX_MTI_STAT_STATN_CONTROL, cfg);
|
|
|
|
val_lo = rpm_read(rpm, 0,
|
|
RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2);
|
|
val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
|
|
rsp->fec_corr_blks = (val_hi << 32 | val_lo);
|
|
|
|
val_lo = rpm_read(rpm, 0,
|
|
RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3);
|
|
val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
|
|
rsp->fec_uncorr_blks = (val_hi << 32 | val_lo);
|
|
}
|
|
|
|
return 0;
|
|
}
|