111 lines
3.9 KiB
C
111 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2018 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_RX_COMMON_H
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#define EFX_RX_COMMON_H
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/* Preferred number of descriptors to fill at once */
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#define EFX_RX_PREFERRED_BATCH 8U
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/* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
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#define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \
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EFX_RX_USR_BUF_SIZE)
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/* Number of RX buffers to recycle pages for. When creating the RX page recycle
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* ring, this number is divided by the number of buffers per page to calculate
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* the number of pages to store in the RX page recycle ring.
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*/
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#define EFX_RECYCLE_RING_SIZE_10G 256
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static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf)
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{
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return page_address(buf->page) + buf->page_offset;
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}
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static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh)
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{
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#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
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return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset));
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#else
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const u8 *data = eh + efx->rx_packet_hash_offset;
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return (u32)data[0] |
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(u32)data[1] << 8 |
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(u32)data[2] << 16 |
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(u32)data[3] << 24;
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#endif
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}
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void efx_siena_rx_slow_fill(struct timer_list *t);
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void efx_siena_recycle_rx_pages(struct efx_channel *channel,
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struct efx_rx_buffer *rx_buf,
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unsigned int n_frags);
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void efx_siena_discard_rx_packet(struct efx_channel *channel,
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struct efx_rx_buffer *rx_buf,
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unsigned int n_frags);
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int efx_siena_probe_rx_queue(struct efx_rx_queue *rx_queue);
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void efx_siena_init_rx_queue(struct efx_rx_queue *rx_queue);
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void efx_siena_fini_rx_queue(struct efx_rx_queue *rx_queue);
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void efx_siena_remove_rx_queue(struct efx_rx_queue *rx_queue);
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static inline void efx_sync_rx_buffer(struct efx_nic *efx,
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struct efx_rx_buffer *rx_buf,
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unsigned int len)
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{
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dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len,
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DMA_FROM_DEVICE);
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}
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void efx_siena_free_rx_buffers(struct efx_rx_queue *rx_queue,
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struct efx_rx_buffer *rx_buf,
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unsigned int num_bufs);
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void efx_siena_rx_config_page_split(struct efx_nic *efx);
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void efx_siena_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue,
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bool atomic);
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void
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efx_siena_rx_packet_gro(struct efx_channel *channel,
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struct efx_rx_buffer *rx_buf,
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unsigned int n_frags, u8 *eh, __wsum csum);
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struct efx_rss_context *efx_siena_alloc_rss_context_entry(struct efx_nic *efx);
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struct efx_rss_context *efx_siena_find_rss_context_entry(struct efx_nic *efx,
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u32 id);
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void efx_siena_free_rss_context_entry(struct efx_rss_context *ctx);
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void efx_siena_set_default_rx_indir_table(struct efx_nic *efx,
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struct efx_rss_context *ctx);
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bool efx_siena_filter_is_mc_recipient(const struct efx_filter_spec *spec);
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bool efx_siena_filter_spec_equal(const struct efx_filter_spec *left,
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const struct efx_filter_spec *right);
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u32 efx_siena_filter_spec_hash(const struct efx_filter_spec *spec);
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#ifdef CONFIG_RFS_ACCEL
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bool efx_siena_rps_check_rule(struct efx_arfs_rule *rule,
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unsigned int filter_idx, bool *force);
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struct efx_arfs_rule *efx_siena_rps_hash_find(struct efx_nic *efx,
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const struct efx_filter_spec *spec);
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void efx_siena_rps_hash_del(struct efx_nic *efx,
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const struct efx_filter_spec *spec);
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int efx_siena_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
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u16 rxq_index, u32 flow_id);
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bool __efx_siena_filter_rfs_expire(struct efx_channel *channel,
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unsigned int quota);
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#endif
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int efx_siena_probe_filters(struct efx_nic *efx);
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void efx_siena_remove_filters(struct efx_nic *efx);
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#endif
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