274 lines
7.2 KiB
C
274 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright Sunplus Technology Co., Ltd.
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* All rights reserved.
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*/
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#include <linux/platform_device.h>
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#include <linux/etherdevice.h>
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#include <linux/netdevice.h>
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#include <linux/bitfield.h>
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#include <linux/spinlock.h>
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#include <linux/of_mdio.h>
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#include "spl2sw_register.h"
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#include "spl2sw_define.h"
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#include "spl2sw_int.h"
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int spl2sw_rx_poll(struct napi_struct *napi, int budget)
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{
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struct spl2sw_common *comm = container_of(napi, struct spl2sw_common, rx_napi);
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struct spl2sw_mac_desc *desc, *h_desc;
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struct net_device_stats *stats;
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struct sk_buff *skb, *new_skb;
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struct spl2sw_skb_info *sinfo;
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int budget_left = budget;
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unsigned long flags;
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u32 rx_pos, pkg_len;
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u32 num, rx_count;
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s32 queue;
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u32 mask;
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int port;
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u32 cmd;
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u32 len;
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/* Process high-priority queue and then low-priority queue. */
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for (queue = 0; queue < RX_DESC_QUEUE_NUM; queue++) {
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rx_pos = comm->rx_pos[queue];
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rx_count = comm->rx_desc_num[queue];
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for (num = 0; num < rx_count && budget_left; num++) {
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sinfo = comm->rx_skb_info[queue] + rx_pos;
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desc = comm->rx_desc[queue] + rx_pos;
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cmd = desc->cmd1;
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if (cmd & RXD_OWN)
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break;
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port = FIELD_GET(RXD_PKT_SP, cmd);
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if (port < MAX_NETDEV_NUM && comm->ndev[port])
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stats = &comm->ndev[port]->stats;
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else
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goto spl2sw_rx_poll_rec_err;
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pkg_len = FIELD_GET(RXD_PKT_LEN, cmd);
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if (unlikely((cmd & RXD_ERR_CODE) || pkg_len < ETH_ZLEN + 4)) {
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stats->rx_length_errors++;
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stats->rx_dropped++;
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goto spl2sw_rx_poll_rec_err;
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}
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dma_unmap_single(&comm->pdev->dev, sinfo->mapping,
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comm->rx_desc_buff_size, DMA_FROM_DEVICE);
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skb = sinfo->skb;
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skb_put(skb, pkg_len - 4); /* Minus FCS */
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skb->ip_summed = CHECKSUM_NONE;
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skb->protocol = eth_type_trans(skb, comm->ndev[port]);
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len = skb->len;
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netif_receive_skb(skb);
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stats->rx_packets++;
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stats->rx_bytes += len;
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/* Allocate a new skb for receiving. */
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new_skb = netdev_alloc_skb(NULL, comm->rx_desc_buff_size);
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if (unlikely(!new_skb)) {
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desc->cmd2 = (rx_pos == comm->rx_desc_num[queue] - 1) ?
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RXD_EOR : 0;
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sinfo->skb = NULL;
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sinfo->mapping = 0;
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desc->addr1 = 0;
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goto spl2sw_rx_poll_alloc_err;
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}
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sinfo->mapping = dma_map_single(&comm->pdev->dev, new_skb->data,
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comm->rx_desc_buff_size,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(&comm->pdev->dev, sinfo->mapping)) {
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dev_kfree_skb_irq(new_skb);
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desc->cmd2 = (rx_pos == comm->rx_desc_num[queue] - 1) ?
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RXD_EOR : 0;
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sinfo->skb = NULL;
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sinfo->mapping = 0;
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desc->addr1 = 0;
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goto spl2sw_rx_poll_alloc_err;
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}
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sinfo->skb = new_skb;
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desc->addr1 = sinfo->mapping;
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spl2sw_rx_poll_rec_err:
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desc->cmd2 = (rx_pos == comm->rx_desc_num[queue] - 1) ?
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RXD_EOR | comm->rx_desc_buff_size :
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comm->rx_desc_buff_size;
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wmb(); /* Set RXD_OWN after other fields are effective. */
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desc->cmd1 = RXD_OWN;
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spl2sw_rx_poll_alloc_err:
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/* Move rx_pos to next position */
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rx_pos = ((rx_pos + 1) == comm->rx_desc_num[queue]) ? 0 : rx_pos + 1;
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budget_left--;
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/* If there are packets in high-priority queue,
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* stop processing low-priority queue.
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*/
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if (queue == 1 && !(h_desc->cmd1 & RXD_OWN))
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break;
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}
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comm->rx_pos[queue] = rx_pos;
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/* Save pointer to last rx descriptor of high-priority queue. */
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if (queue == 0)
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h_desc = comm->rx_desc[queue] + rx_pos;
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}
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spin_lock_irqsave(&comm->int_mask_lock, flags);
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mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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mask &= ~MAC_INT_RX;
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writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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spin_unlock_irqrestore(&comm->int_mask_lock, flags);
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napi_complete(napi);
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return budget - budget_left;
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}
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int spl2sw_tx_poll(struct napi_struct *napi, int budget)
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{
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struct spl2sw_common *comm = container_of(napi, struct spl2sw_common, tx_napi);
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struct spl2sw_skb_info *skbinfo;
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struct net_device_stats *stats;
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int budget_left = budget;
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unsigned long flags;
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u32 tx_done_pos;
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u32 mask;
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u32 cmd;
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int i;
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spin_lock(&comm->tx_lock);
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tx_done_pos = comm->tx_done_pos;
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while (((tx_done_pos != comm->tx_pos) || (comm->tx_desc_full == 1)) && budget_left) {
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cmd = comm->tx_desc[tx_done_pos].cmd1;
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if (cmd & TXD_OWN)
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break;
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skbinfo = &comm->tx_temp_skb_info[tx_done_pos];
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if (unlikely(!skbinfo->skb))
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goto spl2sw_tx_poll_next;
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i = ffs(FIELD_GET(TXD_VLAN, cmd)) - 1;
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if (i < MAX_NETDEV_NUM && comm->ndev[i])
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stats = &comm->ndev[i]->stats;
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else
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goto spl2sw_tx_poll_unmap;
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if (unlikely(cmd & (TXD_ERR_CODE))) {
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stats->tx_errors++;
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} else {
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stats->tx_packets++;
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stats->tx_bytes += skbinfo->len;
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}
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spl2sw_tx_poll_unmap:
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dma_unmap_single(&comm->pdev->dev, skbinfo->mapping, skbinfo->len,
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DMA_TO_DEVICE);
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skbinfo->mapping = 0;
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dev_kfree_skb_irq(skbinfo->skb);
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skbinfo->skb = NULL;
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spl2sw_tx_poll_next:
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/* Move tx_done_pos to next position */
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tx_done_pos = ((tx_done_pos + 1) == TX_DESC_NUM) ? 0 : tx_done_pos + 1;
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if (comm->tx_desc_full == 1)
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comm->tx_desc_full = 0;
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budget_left--;
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}
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comm->tx_done_pos = tx_done_pos;
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if (!comm->tx_desc_full)
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for (i = 0; i < MAX_NETDEV_NUM; i++)
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if (comm->ndev[i])
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if (netif_queue_stopped(comm->ndev[i]))
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netif_wake_queue(comm->ndev[i]);
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spin_unlock(&comm->tx_lock);
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spin_lock_irqsave(&comm->int_mask_lock, flags);
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mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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mask &= ~MAC_INT_TX;
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writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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spin_unlock_irqrestore(&comm->int_mask_lock, flags);
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napi_complete(napi);
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return budget - budget_left;
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}
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irqreturn_t spl2sw_ethernet_interrupt(int irq, void *dev_id)
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{
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struct spl2sw_common *comm = (struct spl2sw_common *)dev_id;
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u32 status;
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u32 mask;
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int i;
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status = readl(comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);
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if (unlikely(!status)) {
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dev_dbg(&comm->pdev->dev, "Interrupt status is null!\n");
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goto spl2sw_ethernet_int_out;
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}
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writel(status, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);
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if (status & MAC_INT_RX) {
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/* Disable RX interrupts. */
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spin_lock(&comm->int_mask_lock);
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mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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mask |= MAC_INT_RX;
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writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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spin_unlock(&comm->int_mask_lock);
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if (unlikely(status & MAC_INT_RX_DES_ERR)) {
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for (i = 0; i < MAX_NETDEV_NUM; i++)
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if (comm->ndev[i]) {
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comm->ndev[i]->stats.rx_fifo_errors++;
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break;
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}
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dev_dbg(&comm->pdev->dev, "Illegal RX Descriptor!\n");
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}
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napi_schedule(&comm->rx_napi);
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}
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if (status & MAC_INT_TX) {
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/* Disable TX interrupts. */
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spin_lock(&comm->int_mask_lock);
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mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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mask |= MAC_INT_TX;
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writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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spin_unlock(&comm->int_mask_lock);
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if (unlikely(status & MAC_INT_TX_DES_ERR)) {
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for (i = 0; i < MAX_NETDEV_NUM; i++)
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if (comm->ndev[i]) {
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comm->ndev[i]->stats.tx_fifo_errors++;
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break;
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}
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dev_dbg(&comm->pdev->dev, "Illegal TX Descriptor Error\n");
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spin_lock(&comm->int_mask_lock);
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mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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mask &= ~MAC_INT_TX;
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writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
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spin_unlock(&comm->int_mask_lock);
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} else {
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napi_schedule(&comm->tx_napi);
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}
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}
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spl2sw_ethernet_int_out:
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return IRQ_HANDLED;
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}
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