227 lines
5.0 KiB
C
227 lines
5.0 KiB
C
/* SPDX-License-Identifier: ISC */
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/*
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* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
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*/
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#ifndef _COREDUMP_H_
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#define _COREDUMP_H_
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#include "core.h"
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#define ATH10K_FW_CRASH_DUMP_VERSION 1
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/**
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* enum ath10k_fw_crash_dump_type - types of data in the dump file
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* @ATH10K_FW_CRASH_DUMP_REGDUMP: Register crash dump in binary format
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*/
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enum ath10k_fw_crash_dump_type {
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ATH10K_FW_CRASH_DUMP_REGISTERS = 0,
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ATH10K_FW_CRASH_DUMP_CE_DATA = 1,
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/* contains multiple struct ath10k_dump_ram_data_hdr */
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ATH10K_FW_CRASH_DUMP_RAM_DATA = 2,
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ATH10K_FW_CRASH_DUMP_MAX,
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};
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struct ath10k_tlv_dump_data {
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/* see ath10k_fw_crash_dump_type above */
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__le32 type;
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/* in bytes */
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__le32 tlv_len;
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/* pad to 32-bit boundaries as needed */
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u8 tlv_data[];
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} __packed;
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struct ath10k_dump_file_data {
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/* dump file information */
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/* "ATH10K-FW-DUMP" */
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char df_magic[16];
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__le32 len;
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/* file dump version */
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__le32 version;
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/* some info we can get from ath10k struct that might help */
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guid_t guid;
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__le32 chip_id;
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/* 0 for now, in place for later hardware */
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__le32 bus_type;
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__le32 target_version;
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__le32 fw_version_major;
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__le32 fw_version_minor;
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__le32 fw_version_release;
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__le32 fw_version_build;
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__le32 phy_capability;
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__le32 hw_min_tx_power;
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__le32 hw_max_tx_power;
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__le32 ht_cap_info;
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__le32 vht_cap_info;
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__le32 num_rf_chains;
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/* firmware version string */
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char fw_ver[ETHTOOL_FWVERS_LEN];
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/* Kernel related information */
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/* time-of-day stamp */
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__le64 tv_sec;
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/* time-of-day stamp, nano-seconds */
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__le64 tv_nsec;
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/* LINUX_VERSION_CODE */
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__le32 kernel_ver_code;
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/* VERMAGIC_STRING */
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char kernel_ver[64];
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/* room for growth w/out changing binary format */
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u8 unused[128];
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/* struct ath10k_tlv_dump_data + more */
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u8 data[];
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} __packed;
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struct ath10k_dump_ram_data_hdr {
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/* enum ath10k_mem_region_type */
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__le32 region_type;
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__le32 start;
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/* length of payload data, not including this header */
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__le32 length;
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u8 data[];
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};
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/* magic number to fill the holes not copied due to sections in regions */
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#define ATH10K_MAGIC_NOT_COPIED 0xAA
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/* part of user space ABI */
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enum ath10k_mem_region_type {
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ATH10K_MEM_REGION_TYPE_REG = 1,
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ATH10K_MEM_REGION_TYPE_DRAM = 2,
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ATH10K_MEM_REGION_TYPE_AXI = 3,
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ATH10K_MEM_REGION_TYPE_IRAM1 = 4,
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ATH10K_MEM_REGION_TYPE_IRAM2 = 5,
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ATH10K_MEM_REGION_TYPE_IOSRAM = 6,
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ATH10K_MEM_REGION_TYPE_IOREG = 7,
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ATH10K_MEM_REGION_TYPE_MSA = 8,
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};
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/* Define a section of the region which should be copied. As not all parts
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* of the memory is possible to copy, for example some of the registers can
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* be like that, sections can be used to define what is safe to copy.
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*
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* To minimize the size of the array, the list must obey the format:
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* '{start0,stop0},{start1,stop1},{start2,stop2}....' The values below must
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* also obey to 'start0 < stop0 < start1 < stop1 < start2 < ...', otherwise
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* we may encounter error in the dump processing.
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*/
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struct ath10k_mem_section {
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u32 start;
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u32 end;
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};
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/* One region of a memory layout. If the sections field is null entire
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* region is copied. If sections is non-null only the areas specified in
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* sections are copied and rest of the areas are filled with
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* ATH10K_MAGIC_NOT_COPIED.
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*/
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struct ath10k_mem_region {
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enum ath10k_mem_region_type type;
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u32 start;
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u32 len;
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const char *name;
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struct {
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const struct ath10k_mem_section *sections;
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u32 size;
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} section_table;
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};
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/* Contains the memory layout of a hardware version identified with the
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* hardware id, split into regions.
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*/
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struct ath10k_hw_mem_layout {
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u32 hw_id;
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u32 hw_rev;
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enum ath10k_bus bus;
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struct {
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const struct ath10k_mem_region *regions;
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int size;
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} region_table;
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};
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/* FIXME: where to put this? */
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extern unsigned long ath10k_coredump_mask;
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#ifdef CONFIG_DEV_COREDUMP
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int ath10k_coredump_submit(struct ath10k *ar);
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struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar);
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int ath10k_coredump_create(struct ath10k *ar);
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int ath10k_coredump_register(struct ath10k *ar);
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void ath10k_coredump_unregister(struct ath10k *ar);
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void ath10k_coredump_destroy(struct ath10k *ar);
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const struct ath10k_hw_mem_layout *_ath10k_coredump_get_mem_layout(struct ath10k *ar);
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const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k *ar);
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#else /* CONFIG_DEV_COREDUMP */
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static inline int ath10k_coredump_submit(struct ath10k *ar)
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{
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return 0;
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}
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static inline struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar)
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{
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return NULL;
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}
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static inline int ath10k_coredump_create(struct ath10k *ar)
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{
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return 0;
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}
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static inline int ath10k_coredump_register(struct ath10k *ar)
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{
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return 0;
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}
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static inline void ath10k_coredump_unregister(struct ath10k *ar)
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{
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}
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static inline void ath10k_coredump_destroy(struct ath10k *ar)
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{
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}
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static inline const struct ath10k_hw_mem_layout *
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ath10k_coredump_get_mem_layout(struct ath10k *ar)
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{
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return NULL;
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}
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static inline const struct ath10k_hw_mem_layout *
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_ath10k_coredump_get_mem_layout(struct ath10k *ar)
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{
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return NULL;
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}
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#endif /* CONFIG_DEV_COREDUMP */
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#endif /* _COREDUMP_H_ */
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