184 lines
5.4 KiB
C
184 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2020-2022 Intel Corporation
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*/
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#ifndef __iwl_trans_queue_tx_h__
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#define __iwl_trans_queue_tx_h__
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#include "iwl-fh.h"
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#include "fw/api/tx.h"
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struct iwl_tso_hdr_page {
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struct page *page;
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u8 *pos;
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};
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static inline dma_addr_t
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iwl_txq_get_first_tb_dma(struct iwl_txq *txq, int idx)
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{
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return txq->first_tb_dma +
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sizeof(struct iwl_pcie_first_tb_buf) * idx;
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}
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static inline u16 iwl_txq_get_cmd_index(const struct iwl_txq *q, u32 index)
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{
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return index & (q->n_window - 1);
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}
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void iwl_txq_gen2_unmap(struct iwl_trans *trans, int txq_id);
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static inline void iwl_wake_queue(struct iwl_trans *trans,
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struct iwl_txq *txq)
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{
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if (test_and_clear_bit(txq->id, trans->txqs.queue_stopped)) {
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IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
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iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
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}
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}
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static inline void *iwl_txq_get_tfd(struct iwl_trans *trans,
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struct iwl_txq *txq, int idx)
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{
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if (trans->trans_cfg->use_tfh)
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idx = iwl_txq_get_cmd_index(txq, idx);
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return (u8 *)txq->tfds + trans->txqs.tfd.size * idx;
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}
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int iwl_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num,
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bool cmd_queue);
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/*
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* We need this inline in case dma_addr_t is only 32-bits - since the
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* hardware is always 64-bit, the issue can still occur in that case,
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* so use u64 for 'phys' here to force the addition in 64-bit.
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*/
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static inline bool iwl_txq_crosses_4g_boundary(u64 phys, u16 len)
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{
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return upper_32_bits(phys) != upper_32_bits(phys + len);
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}
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int iwl_txq_space(struct iwl_trans *trans, const struct iwl_txq *q);
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static inline void iwl_txq_stop(struct iwl_trans *trans, struct iwl_txq *txq)
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{
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if (!test_and_set_bit(txq->id, trans->txqs.queue_stopped)) {
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iwl_op_mode_queue_full(trans->op_mode, txq->id);
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IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
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} else {
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IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
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txq->id);
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}
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}
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/**
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* iwl_txq_inc_wrap - increment queue index, wrap back to beginning
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* @index -- current index
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*/
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static inline int iwl_txq_inc_wrap(struct iwl_trans *trans, int index)
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{
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return ++index &
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(trans->trans_cfg->base_params->max_tfd_queue_size - 1);
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}
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/**
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* iwl_txq_dec_wrap - decrement queue index, wrap back to end
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* @index -- current index
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*/
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static inline int iwl_txq_dec_wrap(struct iwl_trans *trans, int index)
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{
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return --index &
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(trans->trans_cfg->base_params->max_tfd_queue_size - 1);
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}
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static inline bool iwl_txq_used(const struct iwl_txq *q, int i)
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{
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int index = iwl_txq_get_cmd_index(q, i);
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int r = iwl_txq_get_cmd_index(q, q->read_ptr);
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int w = iwl_txq_get_cmd_index(q, q->write_ptr);
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return w >= r ?
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(index >= r && index < w) :
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!(index < r && index >= w);
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}
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void iwl_txq_free_tso_page(struct iwl_trans *trans, struct sk_buff *skb);
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void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq);
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int iwl_txq_gen2_set_tb(struct iwl_trans *trans,
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struct iwl_tfh_tfd *tfd, dma_addr_t addr,
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u16 len);
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void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans,
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struct iwl_cmd_meta *meta,
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struct iwl_tfh_tfd *tfd);
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int iwl_txq_dyn_alloc(struct iwl_trans *trans, u32 flags,
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u32 sta_mask, u8 tid,
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int size, unsigned int timeout);
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int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_device_tx_cmd *dev_cmd, int txq_id);
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void iwl_txq_dyn_free(struct iwl_trans *trans, int queue);
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void iwl_txq_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq);
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void iwl_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq);
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void iwl_txq_gen2_tx_free(struct iwl_trans *trans);
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int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num,
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bool cmd_queue);
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int iwl_txq_gen2_init(struct iwl_trans *trans, int txq_id, int queue_size);
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#ifdef CONFIG_INET
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struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len,
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struct sk_buff *skb);
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#endif
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static inline u8 iwl_txq_gen1_tfd_get_num_tbs(struct iwl_trans *trans,
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void *_tfd)
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{
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struct iwl_tfd *tfd;
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if (trans->trans_cfg->use_tfh) {
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struct iwl_tfh_tfd *tfh_tfd = _tfd;
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return le16_to_cpu(tfh_tfd->num_tbs) & 0x1f;
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}
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tfd = (struct iwl_tfd *)_tfd;
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return tfd->num_tbs & 0x1f;
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}
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static inline u16 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans *trans,
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void *_tfd, u8 idx)
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{
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struct iwl_tfd *tfd;
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struct iwl_tfd_tb *tb;
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if (trans->trans_cfg->use_tfh) {
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struct iwl_tfh_tfd *tfh_tfd = _tfd;
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struct iwl_tfh_tb *tfh_tb = &tfh_tfd->tbs[idx];
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return le16_to_cpu(tfh_tb->tb_len);
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}
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tfd = (struct iwl_tfd *)_tfd;
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tb = &tfd->tbs[idx];
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return le16_to_cpu(tb->hi_n_len) >> 4;
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}
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void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans,
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struct iwl_cmd_meta *meta,
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struct iwl_txq *txq, int index);
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void iwl_txq_gen1_inval_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_txq *txq);
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void iwl_txq_gen1_update_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_txq *txq, u16 byte_cnt,
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int num_tbs);
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void iwl_txq_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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struct sk_buff_head *skbs);
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void iwl_txq_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr);
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void iwl_trans_txq_freeze_timer(struct iwl_trans *trans, unsigned long txqs,
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bool freeze);
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void iwl_txq_progress(struct iwl_txq *txq);
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void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq);
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int iwl_trans_txq_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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#endif /* __iwl_trans_queue_tx_h__ */
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