346 lines
8.3 KiB
C
346 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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* Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/etherdevice.h>
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#include <asm/unaligned.h>
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#include "mt76x0.h"
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#include "eeprom.h"
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#include "../mt76x02_phy.h"
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#define MT_MAP_READS DIV_ROUND_UP(MT_EFUSE_USAGE_MAP_SIZE, 16)
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static int
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mt76x0_efuse_physical_size_check(struct mt76x02_dev *dev)
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{
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u8 data[MT_MAP_READS * 16];
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int ret, i;
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u32 start = 0, end = 0, cnt_free;
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ret = mt76x02_get_efuse_data(dev, MT_EE_USAGE_MAP_START, data,
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sizeof(data), MT_EE_PHYSICAL_READ);
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if (ret)
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return ret;
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for (i = 0; i < MT_EFUSE_USAGE_MAP_SIZE; i++)
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if (!data[i]) {
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if (!start)
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start = MT_EE_USAGE_MAP_START + i;
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end = MT_EE_USAGE_MAP_START + i;
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}
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cnt_free = end - start + 1;
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if (MT_EFUSE_USAGE_MAP_SIZE - cnt_free < 5) {
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dev_err(dev->mt76.dev,
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"driver does not support default EEPROM\n");
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return -EINVAL;
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}
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return 0;
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}
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static void mt76x0_set_chip_cap(struct mt76x02_dev *dev)
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{
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u16 nic_conf0 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
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u16 nic_conf1 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1);
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mt76x02_eeprom_parse_hw_cap(dev);
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dev_dbg(dev->mt76.dev, "2GHz %d 5GHz %d\n",
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dev->mphy.cap.has_2ghz, dev->mphy.cap.has_5ghz);
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if (dev->no_2ghz) {
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dev->mphy.cap.has_2ghz = false;
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dev_dbg(dev->mt76.dev, "mask out 2GHz support\n");
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}
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if (is_mt7630(dev)) {
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dev->mphy.cap.has_5ghz = false;
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dev_dbg(dev->mt76.dev, "mask out 5GHz support\n");
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}
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if (!mt76x02_field_valid(nic_conf1 & 0xff))
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nic_conf1 &= 0xff00;
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if (nic_conf1 & MT_EE_NIC_CONF_1_HW_RF_CTRL)
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dev_dbg(dev->mt76.dev,
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"driver does not support HW RF ctrl\n");
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if (!mt76x02_field_valid(nic_conf0 >> 8))
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return;
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if (FIELD_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 ||
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FIELD_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1)
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dev_err(dev->mt76.dev, "invalid tx-rx stream\n");
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}
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static void mt76x0_set_temp_offset(struct mt76x02_dev *dev)
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{
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u8 val;
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val = mt76x02_eeprom_get(dev, MT_EE_2G_TARGET_POWER) >> 8;
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if (mt76x02_field_valid(val))
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dev->cal.rx.temp_offset = mt76x02_sign_extend(val, 8);
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else
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dev->cal.rx.temp_offset = -10;
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}
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static void mt76x0_set_freq_offset(struct mt76x02_dev *dev)
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{
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struct mt76x02_rx_freq_cal *caldata = &dev->cal.rx;
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u8 val;
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val = mt76x02_eeprom_get(dev, MT_EE_FREQ_OFFSET);
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if (!mt76x02_field_valid(val))
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val = 0;
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caldata->freq_offset = val;
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val = mt76x02_eeprom_get(dev, MT_EE_TSSI_BOUND4) >> 8;
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if (!mt76x02_field_valid(val))
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val = 0;
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caldata->freq_offset -= mt76x02_sign_extend(val, 8);
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}
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void mt76x0_read_rx_gain(struct mt76x02_dev *dev)
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{
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struct ieee80211_channel *chan = dev->mphy.chandef.chan;
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struct mt76x02_rx_freq_cal *caldata = &dev->cal.rx;
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s8 val, lna_5g[3], lna_2g;
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u16 rssi_offset;
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int i;
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mt76x02_get_rx_gain(dev, chan->band, &rssi_offset, &lna_2g, lna_5g);
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caldata->lna_gain = mt76x02_get_lna_gain(dev, &lna_2g, lna_5g, chan);
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for (i = 0; i < ARRAY_SIZE(caldata->rssi_offset); i++) {
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val = rssi_offset >> (8 * i);
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if (val < -10 || val > 10)
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val = 0;
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caldata->rssi_offset[i] = val;
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}
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}
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static s8 mt76x0_get_delta(struct mt76x02_dev *dev)
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{
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struct cfg80211_chan_def *chandef = &dev->mphy.chandef;
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u8 val;
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if (chandef->width == NL80211_CHAN_WIDTH_80) {
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val = mt76x02_eeprom_get(dev, MT_EE_5G_TARGET_POWER) >> 8;
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} else if (chandef->width == NL80211_CHAN_WIDTH_40) {
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u16 data;
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data = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
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if (chandef->chan->band == NL80211_BAND_5GHZ)
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val = data >> 8;
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else
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val = data;
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} else {
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return 0;
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}
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return mt76x02_rate_power_val(val);
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}
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void mt76x0_get_tx_power_per_rate(struct mt76x02_dev *dev,
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struct ieee80211_channel *chan,
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struct mt76x02_rate_power *t)
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{
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bool is_2ghz = chan->band == NL80211_BAND_2GHZ;
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u16 val, addr;
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s8 delta;
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memset(t, 0, sizeof(*t));
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/* cck 1M, 2M, 5.5M, 11M */
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val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_BYRATE_BASE);
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t->cck[0] = t->cck[1] = s6_to_s8(val);
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t->cck[2] = t->cck[3] = s6_to_s8(val >> 8);
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/* ofdm 6M, 9M, 12M, 18M */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 2 : 0x120;
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val = mt76x02_eeprom_get(dev, addr);
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t->ofdm[0] = t->ofdm[1] = s6_to_s8(val);
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t->ofdm[2] = t->ofdm[3] = s6_to_s8(val >> 8);
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/* ofdm 24M, 36M, 48M, 54M */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 4 : 0x122;
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val = mt76x02_eeprom_get(dev, addr);
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t->ofdm[4] = t->ofdm[5] = s6_to_s8(val);
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t->ofdm[6] = t->ofdm[7] = s6_to_s8(val >> 8);
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/* ht-vht mcs 1ss 0, 1, 2, 3 */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 6 : 0x124;
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val = mt76x02_eeprom_get(dev, addr);
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t->ht[0] = t->ht[1] = s6_to_s8(val);
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t->ht[2] = t->ht[3] = s6_to_s8(val >> 8);
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/* ht-vht mcs 1ss 4, 5, 6 */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 8 : 0x126;
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val = mt76x02_eeprom_get(dev, addr);
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t->ht[4] = t->ht[5] = s6_to_s8(val);
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t->ht[6] = t->ht[7] = s6_to_s8(val >> 8);
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/* vht mcs 8, 9 5GHz */
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val = mt76x02_eeprom_get(dev, 0x12c);
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t->vht[0] = s6_to_s8(val);
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t->vht[1] = s6_to_s8(val >> 8);
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delta = mt76x0_tssi_enabled(dev) ? 0 : mt76x0_get_delta(dev);
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mt76x02_add_rate_power_offset(t, delta);
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}
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void mt76x0_get_power_info(struct mt76x02_dev *dev,
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struct ieee80211_channel *chan, s8 *tp)
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{
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static const struct mt76x0_chan_map {
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u8 chan;
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u8 offset;
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} chan_map[] = {
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{ 2, 0 }, { 4, 2 }, { 6, 4 }, { 8, 6 },
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{ 10, 8 }, { 12, 10 }, { 14, 12 }, { 38, 0 },
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{ 44, 2 }, { 48, 4 }, { 54, 6 }, { 60, 8 },
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{ 64, 10 }, { 102, 12 }, { 108, 14 }, { 112, 16 },
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{ 118, 18 }, { 124, 20 }, { 128, 22 }, { 134, 24 },
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{ 140, 26 }, { 151, 28 }, { 157, 30 }, { 161, 32 },
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{ 167, 34 }, { 171, 36 }, { 175, 38 },
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};
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u8 offset, addr;
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int i, idx = 0;
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u16 data;
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if (mt76x0_tssi_enabled(dev)) {
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s8 target_power;
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if (chan->band == NL80211_BAND_5GHZ)
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data = mt76x02_eeprom_get(dev, MT_EE_5G_TARGET_POWER);
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else
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data = mt76x02_eeprom_get(dev, MT_EE_2G_TARGET_POWER);
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target_power = (data & 0xff) - dev->rate_power.ofdm[7];
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*tp = target_power + mt76x0_get_delta(dev);
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return;
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}
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for (i = 0; i < ARRAY_SIZE(chan_map); i++) {
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if (chan->hw_value <= chan_map[i].chan) {
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idx = (chan->hw_value == chan_map[i].chan);
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offset = chan_map[i].offset;
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break;
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}
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}
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if (i == ARRAY_SIZE(chan_map))
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offset = chan_map[0].offset;
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if (chan->band == NL80211_BAND_2GHZ) {
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addr = MT_EE_TX_POWER_DELTA_BW80 + offset;
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} else {
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switch (chan->hw_value) {
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case 42:
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offset = 2;
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break;
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case 58:
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offset = 8;
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break;
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case 106:
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offset = 14;
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break;
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case 122:
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offset = 20;
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break;
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case 155:
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offset = 30;
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break;
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default:
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break;
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}
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addr = MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE + 2 + offset;
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}
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data = mt76x02_eeprom_get(dev, addr);
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*tp = data >> (8 * idx);
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if (*tp < 0 || *tp > 0x3f)
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*tp = 5;
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}
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static int mt76x0_check_eeprom(struct mt76x02_dev *dev)
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{
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u16 val;
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val = get_unaligned_le16(dev->mt76.eeprom.data);
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if (!val)
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val = get_unaligned_le16(dev->mt76.eeprom.data +
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MT_EE_PCI_ID);
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switch (val) {
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case 0x7650:
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case 0x7610:
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return 0;
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default:
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dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n",
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val);
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return -EINVAL;
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}
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}
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static int mt76x0_load_eeprom(struct mt76x02_dev *dev)
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{
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int found;
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found = mt76_eeprom_init(&dev->mt76, MT76X0_EEPROM_SIZE);
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if (found < 0)
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return found;
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if (found && !mt76x0_check_eeprom(dev))
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return 0;
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found = mt76x0_efuse_physical_size_check(dev);
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if (found < 0)
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return found;
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return mt76x02_get_efuse_data(dev, 0, dev->mt76.eeprom.data,
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MT76X0_EEPROM_SIZE, MT_EE_READ);
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}
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int mt76x0_eeprom_init(struct mt76x02_dev *dev)
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{
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u8 version, fae;
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u16 data;
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int err;
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err = mt76x0_load_eeprom(dev);
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if (err < 0)
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return err;
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data = mt76x02_eeprom_get(dev, MT_EE_VERSION);
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version = data >> 8;
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fae = data;
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if (version > MT76X0U_EE_MAX_VER)
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dev_warn(dev->mt76.dev,
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"Warning: unsupported EEPROM version %02hhx\n",
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version);
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dev_info(dev->mt76.dev, "EEPROM ver:%02hhx fae:%02hhx\n",
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version, fae);
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memcpy(dev->mphy.macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
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ETH_ALEN);
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mt76_eeprom_override(&dev->mphy);
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mt76x02_mac_setaddr(dev, dev->mphy.macaddr);
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mt76x0_set_chip_cap(dev);
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mt76x0_set_freq_offset(dev);
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mt76x0_set_temp_offset(dev);
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return 0;
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}
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MODULE_LICENSE("Dual BSD/GPL");
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