317 lines
8.8 KiB
C
317 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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*/
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#include "mt7601u.h"
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#include "trace.h"
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enum mt76_txq_id {
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MT_TXQ_VO = IEEE80211_AC_VO,
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MT_TXQ_VI = IEEE80211_AC_VI,
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MT_TXQ_BE = IEEE80211_AC_BE,
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MT_TXQ_BK = IEEE80211_AC_BK,
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MT_TXQ_PSD,
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MT_TXQ_MCU,
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__MT_TXQ_MAX
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};
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/* Hardware uses mirrored order of queues with Q0 having the highest priority */
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static u8 q2hwq(u8 q)
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{
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return q ^ 0x3;
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}
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/* Take mac80211 Q id from the skb and translate it to hardware Q id */
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static u8 skb2q(struct sk_buff *skb)
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{
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int qid = skb_get_queue_mapping(skb);
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if (WARN_ON(qid >= MT_TXQ_PSD)) {
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qid = MT_TXQ_BE;
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skb_set_queue_mapping(skb, qid);
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}
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return q2hwq(qid);
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}
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/* Note: TX retry reporting is a bit broken.
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* Retries are reported only once per AMPDU and often come a frame early
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* i.e. they are reported in the last status preceding the AMPDU. Apart
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* from the fact that it's hard to know the length of the AMPDU (which is
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* required to know to how many consecutive frames retries should be
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* applied), if status comes early on full FIFO it gets lost and retries
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* of the whole AMPDU become invisible.
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* As a work-around encode the desired rate in PKT_ID of TX descriptor
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* and based on that guess the retries (every rate is tried once).
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* Only downside here is that for MCS0 we have to rely solely on
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* transmission failures as no retries can ever be reported.
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* Not having to read EXT_FIFO has a nice effect of doubling the number
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* of reports which can be fetched.
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* Also the vendor driver never uses the EXT_FIFO register so it may be
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* undertested.
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*/
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static u8 mt7601u_tx_pktid_enc(struct mt7601u_dev *dev, u8 rate, bool is_probe)
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{
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u8 encoded = (rate + 1) + is_probe * 8;
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/* Because PKT_ID 0 disables status reporting only 15 values are
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* available but 16 are needed (8 MCS * 2 for encoding is_probe)
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* - we need to cram together two rates. MCS0 and MCS7 with is_probe
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* share PKT_ID 9.
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*/
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if (is_probe && rate == 7)
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return encoded - 7;
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return encoded;
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}
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static void
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mt7601u_tx_pktid_dec(struct mt7601u_dev *dev, struct mt76_tx_status *stat)
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{
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u8 req_rate = stat->pktid;
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u8 eff_rate = stat->rate & 0x7;
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req_rate -= 1;
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if (req_rate > 7) {
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stat->is_probe = true;
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req_rate -= 8;
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/* Decide between MCS0 and MCS7 which share pktid 9 */
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if (!req_rate && eff_rate)
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req_rate = 7;
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}
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stat->retry = req_rate - eff_rate;
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}
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static void mt7601u_tx_skb_remove_dma_overhead(struct sk_buff *skb,
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struct ieee80211_tx_info *info)
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{
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int pkt_len = (unsigned long)info->status.status_driver_data[0];
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skb_pull(skb, sizeof(struct mt76_txwi) + 4);
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if (ieee80211_get_hdrlen_from_skb(skb) % 4)
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mt76_remove_hdr_pad(skb);
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skb_trim(skb, pkt_len);
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}
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void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb)
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{
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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mt7601u_tx_skb_remove_dma_overhead(skb, info);
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ieee80211_tx_info_clear_status(info);
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info->status.rates[0].idx = -1;
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info->flags |= IEEE80211_TX_STAT_ACK;
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spin_lock_bh(&dev->mac_lock);
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ieee80211_tx_status(dev->hw, skb);
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spin_unlock_bh(&dev->mac_lock);
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}
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static int mt7601u_skb_rooms(struct mt7601u_dev *dev, struct sk_buff *skb)
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{
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int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
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u32 need_head;
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need_head = sizeof(struct mt76_txwi) + 4;
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if (hdr_len % 4)
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need_head += 2;
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return skb_cow(skb, need_head);
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}
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static struct mt76_txwi *
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mt7601u_push_txwi(struct mt7601u_dev *dev, struct sk_buff *skb,
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struct ieee80211_sta *sta, struct mt76_wcid *wcid,
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int pkt_len)
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{
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ieee80211_tx_rate *rate = &info->control.rates[0];
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struct mt76_txwi *txwi;
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unsigned long flags;
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bool is_probe;
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u32 pkt_id;
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u16 rate_ctl;
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u8 nss;
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txwi = skb_push(skb, sizeof(struct mt76_txwi));
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memset(txwi, 0, sizeof(*txwi));
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if (!wcid->tx_rate_set)
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ieee80211_get_tx_rates(info->control.vif, sta, skb,
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info->control.rates, 1);
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spin_lock_irqsave(&dev->lock, flags);
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if (rate->idx < 0 || !rate->count)
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rate_ctl = wcid->tx_rate;
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else
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rate_ctl = mt76_mac_tx_rate_val(dev, rate, &nss);
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spin_unlock_irqrestore(&dev->lock, flags);
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txwi->rate_ctl = cpu_to_le16(rate_ctl);
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if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
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txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
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if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
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txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
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if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
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u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
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ba_size <<= sta->deflink.ht_cap.ampdu_factor;
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ba_size = min_t(int, 63, ba_size);
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if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
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ba_size = 0;
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txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
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txwi->flags =
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cpu_to_le16(MT_TXWI_FLAGS_AMPDU |
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FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY,
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sta->deflink.ht_cap.ampdu_density));
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if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
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txwi->flags = 0;
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}
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txwi->wcid = wcid->idx;
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is_probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
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pkt_id = mt7601u_tx_pktid_enc(dev, rate_ctl & 0x7, is_probe);
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pkt_len |= FIELD_PREP(MT_TXWI_LEN_PKTID, pkt_id);
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txwi->len_ctl = cpu_to_le16(pkt_len);
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return txwi;
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}
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void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
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struct sk_buff *skb)
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{
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct mt7601u_dev *dev = hw->priv;
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struct ieee80211_vif *vif = info->control.vif;
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struct ieee80211_sta *sta = control->sta;
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struct mt76_sta *msta = NULL;
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struct mt76_wcid *wcid = dev->mon_wcid;
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struct mt76_txwi *txwi;
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int pkt_len = skb->len;
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int hw_q = skb2q(skb);
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BUILD_BUG_ON(ARRAY_SIZE(info->status.status_driver_data) < 1);
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info->status.status_driver_data[0] = (void *)(unsigned long)pkt_len;
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if (mt7601u_skb_rooms(dev, skb) || mt76_insert_hdr_pad(skb)) {
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ieee80211_free_txskb(dev->hw, skb);
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return;
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}
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if (sta) {
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msta = (struct mt76_sta *) sta->drv_priv;
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wcid = &msta->wcid;
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} else if (vif) {
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struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
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wcid = &mvif->group_wcid;
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}
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txwi = mt7601u_push_txwi(dev, skb, sta, wcid, pkt_len);
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if (mt7601u_dma_enqueue_tx(dev, skb, wcid, hw_q))
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return;
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trace_mt_tx(dev, skb, msta, txwi);
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}
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void mt7601u_tx_stat(struct work_struct *work)
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{
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struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
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stat_work.work);
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struct mt76_tx_status stat;
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unsigned long flags;
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int cleaned = 0;
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while (!test_bit(MT7601U_STATE_REMOVED, &dev->state)) {
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stat = mt7601u_mac_fetch_tx_status(dev);
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if (!stat.valid)
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break;
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mt7601u_tx_pktid_dec(dev, &stat);
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mt76_send_tx_status(dev, &stat);
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cleaned++;
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}
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trace_mt_tx_status_cleaned(dev, cleaned);
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spin_lock_irqsave(&dev->tx_lock, flags);
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if (cleaned)
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queue_delayed_work(dev->stat_wq, &dev->stat_work,
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msecs_to_jiffies(10));
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else if (test_and_clear_bit(MT7601U_STATE_MORE_STATS, &dev->state))
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queue_delayed_work(dev->stat_wq, &dev->stat_work,
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msecs_to_jiffies(20));
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else
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clear_bit(MT7601U_STATE_READING_STATS, &dev->state);
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spin_unlock_irqrestore(&dev->tx_lock, flags);
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}
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int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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unsigned int link_id, u16 queue,
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const struct ieee80211_tx_queue_params *params)
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{
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struct mt7601u_dev *dev = hw->priv;
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u8 cw_min = 5, cw_max = 10, hw_q = q2hwq(queue);
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u32 val;
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/* TODO: should we do funny things with the parameters?
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* See what mt7601u_set_default_edca() used to do in init.c.
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*/
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if (params->cw_min)
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cw_min = fls(params->cw_min);
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if (params->cw_max)
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cw_max = fls(params->cw_max);
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WARN_ON(params->txop > 0xff);
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WARN_ON(params->aifs > 0xf);
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WARN_ON(cw_min > 0xf);
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WARN_ON(cw_max > 0xf);
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val = FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) |
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FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) |
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FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max);
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/* TODO: based on user-controlled EnableTxBurst var vendor drv sets
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* a really long txop on AC0 (see connect.c:2009) but only on
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* connect? When not connected should be 0.
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*/
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if (!hw_q)
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val |= 0x60;
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else
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val |= FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop);
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mt76_wr(dev, MT_EDCA_CFG_AC(hw_q), val);
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val = mt76_rr(dev, MT_WMM_TXOP(hw_q));
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val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(hw_q));
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val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q);
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mt76_wr(dev, MT_WMM_TXOP(hw_q), val);
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val = mt76_rr(dev, MT_WMM_AIFSN);
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val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(hw_q));
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val |= params->aifs << MT_WMM_AIFSN_SHIFT(hw_q);
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mt76_wr(dev, MT_WMM_AIFSN, val);
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val = mt76_rr(dev, MT_WMM_CWMIN);
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val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(hw_q));
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val |= cw_min << MT_WMM_CWMIN_SHIFT(hw_q);
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mt76_wr(dev, MT_WMM_CWMIN, val);
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val = mt76_rr(dev, MT_WMM_CWMAX);
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val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(hw_q));
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val |= cw_max << MT_WMM_CWMAX_SHIFT(hw_q);
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mt76_wr(dev, MT_WMM_CWMAX, val);
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return 0;
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}
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