310 lines
7.1 KiB
C
310 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Low-level device IO routines for ST-Ericsson CW1200 drivers
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*
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* Copyright (c) 2010, ST-Ericsson
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* Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
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*
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* Based on:
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* ST-Ericsson UMAC CW1200 driver, which is
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* Copyright (c) 2010, ST-Ericsson
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* Author: Ajitpal Singh <ajitpal.singh@lockless.no>
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*/
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#include <linux/types.h>
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#include "cw1200.h"
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#include "hwio.h"
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#include "hwbus.h"
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/* Sdio addr is 4*spi_addr */
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#define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2)
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#define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \
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((((buf_id) & 0x1F) << 7) \
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| (((mpf) & 1) << 6) \
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| (((rfu) & 1) << 5) \
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| (((reg_id_ofs) & 0x1F) << 0))
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#define MAX_RETRY 3
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static int __cw1200_reg_read(struct cw1200_common *priv, u16 addr,
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void *buf, size_t buf_len, int buf_id)
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{
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u16 addr_sdio;
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u32 sdio_reg_addr_17bit;
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/* Check if buffer is aligned to 4 byte boundary */
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if (WARN_ON(((unsigned long)buf & 3) && (buf_len > 4))) {
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pr_err("buffer is not aligned.\n");
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return -EINVAL;
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}
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/* Convert to SDIO Register Address */
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addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
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sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
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return priv->hwbus_ops->hwbus_memcpy_fromio(priv->hwbus_priv,
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sdio_reg_addr_17bit,
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buf, buf_len);
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}
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static int __cw1200_reg_write(struct cw1200_common *priv, u16 addr,
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const void *buf, size_t buf_len, int buf_id)
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{
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u16 addr_sdio;
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u32 sdio_reg_addr_17bit;
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/* Convert to SDIO Register Address */
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addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
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sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
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return priv->hwbus_ops->hwbus_memcpy_toio(priv->hwbus_priv,
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sdio_reg_addr_17bit,
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buf, buf_len);
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}
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static inline int __cw1200_reg_read_32(struct cw1200_common *priv,
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u16 addr, u32 *val)
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{
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__le32 tmp;
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int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
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*val = le32_to_cpu(tmp);
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return i;
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}
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static inline int __cw1200_reg_write_32(struct cw1200_common *priv,
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u16 addr, u32 val)
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{
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__le32 tmp = cpu_to_le32(val);
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return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
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}
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static inline int __cw1200_reg_read_16(struct cw1200_common *priv,
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u16 addr, u16 *val)
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{
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__le16 tmp;
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int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
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*val = le16_to_cpu(tmp);
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return i;
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}
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static inline int __cw1200_reg_write_16(struct cw1200_common *priv,
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u16 addr, u16 val)
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{
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__le16 tmp = cpu_to_le16(val);
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return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
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}
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int cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf,
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size_t buf_len)
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{
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int ret;
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priv->hwbus_ops->lock(priv->hwbus_priv);
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ret = __cw1200_reg_read(priv, addr, buf, buf_len, 0);
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priv->hwbus_ops->unlock(priv->hwbus_priv);
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return ret;
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}
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int cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf,
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size_t buf_len)
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{
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int ret;
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priv->hwbus_ops->lock(priv->hwbus_priv);
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ret = __cw1200_reg_write(priv, addr, buf, buf_len, 0);
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priv->hwbus_ops->unlock(priv->hwbus_priv);
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return ret;
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}
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int cw1200_data_read(struct cw1200_common *priv, void *buf, size_t buf_len)
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{
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int ret, retry = 1;
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int buf_id_rx = priv->buf_id_rx;
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priv->hwbus_ops->lock(priv->hwbus_priv);
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while (retry <= MAX_RETRY) {
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ret = __cw1200_reg_read(priv,
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ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
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buf_len, buf_id_rx + 1);
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if (!ret) {
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buf_id_rx = (buf_id_rx + 1) & 3;
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priv->buf_id_rx = buf_id_rx;
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break;
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} else {
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retry++;
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mdelay(1);
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pr_err("error :[%d]\n", ret);
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}
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}
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priv->hwbus_ops->unlock(priv->hwbus_priv);
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return ret;
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}
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int cw1200_data_write(struct cw1200_common *priv, const void *buf,
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size_t buf_len)
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{
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int ret, retry = 1;
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int buf_id_tx = priv->buf_id_tx;
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priv->hwbus_ops->lock(priv->hwbus_priv);
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while (retry <= MAX_RETRY) {
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ret = __cw1200_reg_write(priv,
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ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
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buf_len, buf_id_tx);
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if (!ret) {
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buf_id_tx = (buf_id_tx + 1) & 31;
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priv->buf_id_tx = buf_id_tx;
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break;
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} else {
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retry++;
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mdelay(1);
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pr_err("error :[%d]\n", ret);
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}
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}
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priv->hwbus_ops->unlock(priv->hwbus_priv);
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return ret;
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}
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int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
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size_t buf_len, u32 prefetch, u16 port_addr)
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{
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u32 val32 = 0;
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int i, ret;
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if ((buf_len / 2) >= 0x1000) {
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pr_err("Can't read more than 0xfff words.\n");
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return -EINVAL;
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}
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priv->hwbus_ops->lock(priv->hwbus_priv);
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/* Write address */
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ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
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if (ret < 0) {
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pr_err("Can't write address register.\n");
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goto out;
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}
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/* Read CONFIG Register Value - We will read 32 bits */
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ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
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if (ret < 0) {
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pr_err("Can't read config register.\n");
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goto out;
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}
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/* Set PREFETCH bit */
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ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID,
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val32 | prefetch);
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if (ret < 0) {
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pr_err("Can't write prefetch bit.\n");
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goto out;
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}
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/* Check for PRE-FETCH bit to be cleared */
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for (i = 0; i < 20; i++) {
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ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
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if (ret < 0) {
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pr_err("Can't check prefetch bit.\n");
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goto out;
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}
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if (!(val32 & prefetch))
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break;
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mdelay(i);
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}
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if (val32 & prefetch) {
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pr_err("Prefetch bit is not cleared.\n");
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goto out;
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}
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/* Read data port */
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ret = __cw1200_reg_read(priv, port_addr, buf, buf_len, 0);
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if (ret < 0) {
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pr_err("Can't read data port.\n");
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goto out;
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}
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out:
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priv->hwbus_ops->unlock(priv->hwbus_priv);
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return ret;
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}
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int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
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size_t buf_len)
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{
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int ret;
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if ((buf_len / 2) >= 0x1000) {
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pr_err("Can't write more than 0xfff words.\n");
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return -EINVAL;
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}
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priv->hwbus_ops->lock(priv->hwbus_priv);
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/* Write address */
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ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
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if (ret < 0) {
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pr_err("Can't write address register.\n");
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goto out;
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}
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/* Write data port */
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ret = __cw1200_reg_write(priv, ST90TDS_SRAM_DPORT_REG_ID,
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buf, buf_len, 0);
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if (ret < 0) {
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pr_err("Can't write data port.\n");
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goto out;
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}
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out:
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priv->hwbus_ops->unlock(priv->hwbus_priv);
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return ret;
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}
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int __cw1200_irq_enable(struct cw1200_common *priv, int enable)
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{
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u32 val32;
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u16 val16;
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int ret;
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if (HIF_8601_SILICON == priv->hw_type) {
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ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
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if (ret < 0) {
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pr_err("Can't read config register.\n");
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return ret;
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}
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if (enable)
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val32 |= ST90TDS_CONF_IRQ_RDY_ENABLE;
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else
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val32 &= ~ST90TDS_CONF_IRQ_RDY_ENABLE;
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ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val32);
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if (ret < 0) {
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pr_err("Can't write config register.\n");
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return ret;
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}
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} else {
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ret = __cw1200_reg_read_16(priv, ST90TDS_CONFIG_REG_ID, &val16);
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if (ret < 0) {
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pr_err("Can't read control register.\n");
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return ret;
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}
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if (enable)
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val16 |= ST90TDS_CONT_IRQ_RDY_ENABLE;
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else
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val16 &= ~ST90TDS_CONT_IRQ_RDY_ENABLE;
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ret = __cw1200_reg_write_16(priv, ST90TDS_CONFIG_REG_ID, val16);
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if (ret < 0) {
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pr_err("Can't write control register.\n");
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return ret;
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}
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}
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return 0;
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}
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