593 lines
16 KiB
C
593 lines
16 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/ntb.h>
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#include <linux/log2.h>
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#include "ntb_hw_intel.h"
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#include "ntb_hw_gen1.h"
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#include "ntb_hw_gen3.h"
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#include "ntb_hw_gen4.h"
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static int gen4_poll_link(struct intel_ntb_dev *ndev);
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static int gen4_link_is_up(struct intel_ntb_dev *ndev);
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static const struct intel_ntb_reg gen4_reg = {
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.poll_link = gen4_poll_link,
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.link_is_up = gen4_link_is_up,
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.db_ioread = gen3_db_ioread,
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.db_iowrite = gen3_db_iowrite,
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.db_size = sizeof(u32),
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.ntb_ctl = GEN4_NTBCNTL_OFFSET,
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.mw_bar = {2, 4},
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};
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static const struct intel_ntb_alt_reg gen4_pri_reg = {
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.db_clear = GEN4_IM_INT_STATUS_OFFSET,
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.db_mask = GEN4_IM_INT_DISABLE_OFFSET,
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.spad = GEN4_IM_SPAD_OFFSET,
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};
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static const struct intel_ntb_xlat_reg gen4_sec_xlat = {
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.bar2_limit = GEN4_IM23XLMT_OFFSET,
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.bar2_xlat = GEN4_IM23XBASE_OFFSET,
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.bar2_idx = GEN4_IM23XBASEIDX_OFFSET,
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};
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static const struct intel_ntb_alt_reg gen4_b2b_reg = {
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.db_bell = GEN4_IM_DOORBELL_OFFSET,
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.spad = GEN4_EM_SPAD_OFFSET,
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};
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static int gen4_poll_link(struct intel_ntb_dev *ndev)
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{
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u16 reg_val;
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/*
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* We need to write to DLLSCS bit in the SLOTSTS before we
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* can clear the hardware link interrupt on ICX NTB.
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*/
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iowrite16(GEN4_SLOTSTS_DLLSCS, ndev->self_mmio + GEN4_SLOTSTS);
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ndev->reg->db_iowrite(ndev->db_link_mask,
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ndev->self_mmio +
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ndev->self_reg->db_clear);
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reg_val = ioread16(ndev->self_mmio + GEN4_LINK_STATUS_OFFSET);
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if (reg_val == ndev->lnk_sta)
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return 0;
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ndev->lnk_sta = reg_val;
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return 1;
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}
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static int gen4_link_is_up(struct intel_ntb_dev *ndev)
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{
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return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);
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}
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static int gen4_init_isr(struct intel_ntb_dev *ndev)
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{
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int i;
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/*
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* The MSIX vectors and the interrupt status bits are not lined up
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* on Gen3 (Skylake) and Gen4. By default the link status bit is bit
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* 32, however it is by default MSIX vector0. We need to fixup to
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* line them up. The vectors at reset is 1-32,0. We need to reprogram
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* to 0-32.
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*/
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for (i = 0; i < GEN4_DB_MSIX_VECTOR_COUNT; i++)
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iowrite8(i, ndev->self_mmio + GEN4_INTVEC_OFFSET + i);
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return ndev_init_isr(ndev, GEN4_DB_MSIX_VECTOR_COUNT,
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GEN4_DB_MSIX_VECTOR_COUNT,
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GEN4_DB_MSIX_VECTOR_SHIFT,
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GEN4_DB_TOTAL_SHIFT);
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}
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static int gen4_setup_b2b_mw(struct intel_ntb_dev *ndev,
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const struct intel_b2b_addr *addr,
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const struct intel_b2b_addr *peer_addr)
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{
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struct pci_dev *pdev;
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void __iomem *mmio;
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phys_addr_t bar_addr;
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pdev = ndev->ntb.pdev;
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mmio = ndev->self_mmio;
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/* setup incoming bar limits == base addrs (zero length windows) */
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bar_addr = addr->bar2_addr64;
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iowrite64(bar_addr, mmio + GEN4_IM23XLMT_OFFSET);
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bar_addr = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IM23XLMT %#018llx\n", bar_addr);
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bar_addr = addr->bar4_addr64;
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iowrite64(bar_addr, mmio + GEN4_IM45XLMT_OFFSET);
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bar_addr = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IM45XLMT %#018llx\n", bar_addr);
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/* zero incoming translation addrs */
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iowrite64(0, mmio + GEN4_IM23XBASE_OFFSET);
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iowrite64(0, mmio + GEN4_IM45XBASE_OFFSET);
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ndev->peer_mmio = ndev->self_mmio;
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return 0;
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}
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static int gen4_init_ntb(struct intel_ntb_dev *ndev)
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{
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int rc;
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ndev->mw_count = XEON_MW_COUNT;
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ndev->spad_count = GEN4_SPAD_COUNT;
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ndev->db_count = GEN4_DB_COUNT;
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ndev->db_link_mask = GEN4_DB_LINK_BIT;
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ndev->self_reg = &gen4_pri_reg;
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ndev->xlat_reg = &gen4_sec_xlat;
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ndev->peer_reg = &gen4_b2b_reg;
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if (ndev->ntb.topo == NTB_TOPO_B2B_USD)
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rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_dsd_addr,
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&xeon_b2b_usd_addr);
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else
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rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_usd_addr,
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&xeon_b2b_dsd_addr);
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if (rc)
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return rc;
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ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
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ndev->reg->db_iowrite(ndev->db_valid_mask,
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ndev->self_mmio +
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ndev->self_reg->db_mask);
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return 0;
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}
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static enum ntb_topo gen4_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
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{
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switch (ppd & GEN4_PPD_TOPO_MASK) {
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case GEN4_PPD_TOPO_B2B_USD:
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return NTB_TOPO_B2B_USD;
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case GEN4_PPD_TOPO_B2B_DSD:
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return NTB_TOPO_B2B_DSD;
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}
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return NTB_TOPO_NONE;
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}
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static enum ntb_topo spr_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
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{
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switch (ppd & SPR_PPD_TOPO_MASK) {
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case SPR_PPD_TOPO_B2B_USD:
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return NTB_TOPO_B2B_USD;
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case SPR_PPD_TOPO_B2B_DSD:
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return NTB_TOPO_B2B_DSD;
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}
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return NTB_TOPO_NONE;
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}
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int gen4_init_dev(struct intel_ntb_dev *ndev)
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{
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struct pci_dev *pdev = ndev->ntb.pdev;
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u32 ppd1/*, ppd0*/;
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u16 lnkctl;
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int rc;
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ndev->reg = &gen4_reg;
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if (pdev_is_ICX(pdev)) {
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ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN;
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ndev->hwerr_flags |= NTB_HWERR_LTR_BAD;
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}
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ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
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if (pdev_is_ICX(pdev))
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ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
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else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev))
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ndev->ntb.topo = spr_ppd_topo(ndev, ppd1);
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dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,
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ntb_topo_string(ndev->ntb.topo));
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if (ndev->ntb.topo == NTB_TOPO_NONE)
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return -EINVAL;
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rc = gen4_init_ntb(ndev);
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if (rc)
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return rc;
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/* init link setup */
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lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
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lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
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iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
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return gen4_init_isr(ndev);
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}
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ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
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size_t count, loff_t *offp)
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{
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struct intel_ntb_dev *ndev;
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void __iomem *mmio;
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char *buf;
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size_t buf_size;
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ssize_t ret, off;
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union { u64 v64; u32 v32; u16 v16; } u;
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ndev = filp->private_data;
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mmio = ndev->self_mmio;
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buf_size = min(count, 0x800ul);
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buf = kmalloc(buf_size, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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off = 0;
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off += scnprintf(buf + off, buf_size - off,
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"NTB Device Information:\n");
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off += scnprintf(buf + off, buf_size - off,
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"Connection Topology -\t%s\n",
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ntb_topo_string(ndev->ntb.topo));
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off += scnprintf(buf + off, buf_size - off,
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"NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);
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off += scnprintf(buf + off, buf_size - off,
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"LNK STA (cached) -\t\t%#06x\n", ndev->lnk_sta);
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if (!ndev->reg->link_is_up(ndev))
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off += scnprintf(buf + off, buf_size - off,
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"Link Status -\t\tDown\n");
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else {
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off += scnprintf(buf + off, buf_size - off,
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"Link Status -\t\tUp\n");
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off += scnprintf(buf + off, buf_size - off,
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"Link Speed -\t\tPCI-E Gen %u\n",
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NTB_LNK_STA_SPEED(ndev->lnk_sta));
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off += scnprintf(buf + off, buf_size - off,
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"Link Width -\t\tx%u\n",
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NTB_LNK_STA_WIDTH(ndev->lnk_sta));
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}
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off += scnprintf(buf + off, buf_size - off,
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"Memory Window Count -\t%u\n", ndev->mw_count);
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off += scnprintf(buf + off, buf_size - off,
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"Scratchpad Count -\t%u\n", ndev->spad_count);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Count -\t%u\n", ndev->db_count);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Vector Count -\t%u\n", ndev->db_vec_count);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);
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u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Mask -\t\t%#llx\n", u.v64);
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Incoming XLAT:\n");
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u.v64 = ioread64(mmio + GEN4_IM23XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IM23XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN4_IM45XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IM45XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IM23XLMT -\t\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IM45XLMT -\t\t\t%#018llx\n", u.v64);
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Statistics:\n");
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Hardware Errors:\n");
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if (!pci_read_config_word(ndev->ntb.pdev,
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GEN4_DEVSTS_OFFSET, &u.v16))
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off += scnprintf(buf + off, buf_size - off,
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"DEVSTS -\t\t%#06x\n", u.v16);
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u.v16 = ioread16(mmio + GEN4_LINK_STATUS_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"LNKSTS -\t\t%#06x\n", u.v16);
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if (!pci_read_config_dword(ndev->ntb.pdev,
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GEN4_UNCERRSTS_OFFSET, &u.v32))
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off += scnprintf(buf + off, buf_size - off,
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"UNCERRSTS -\t\t%#06x\n", u.v32);
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if (!pci_read_config_dword(ndev->ntb.pdev,
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GEN4_CORERRSTS_OFFSET, &u.v32))
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off += scnprintf(buf + off, buf_size - off,
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"CORERRSTS -\t\t%#06x\n", u.v32);
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ret = simple_read_from_buffer(ubuf, count, offp, buf, off);
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kfree(buf);
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return ret;
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}
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static int intel_ntb4_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
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dma_addr_t addr, resource_size_t size)
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{
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struct intel_ntb_dev *ndev = ntb_ndev(ntb);
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unsigned long xlat_reg, limit_reg, idx_reg;
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unsigned short base_idx, reg_val16;
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resource_size_t bar_size, mw_size;
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void __iomem *mmio;
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u64 base, limit, reg_val;
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int bar;
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if (pidx != NTB_DEF_PEER_IDX)
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return -EINVAL;
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if (idx >= ndev->b2b_idx && !ndev->b2b_off)
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idx += 1;
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bar = ndev_mw_to_bar(ndev, idx);
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if (bar < 0)
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return bar;
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bar_size = pci_resource_len(ndev->ntb.pdev, bar);
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if (idx == ndev->b2b_idx)
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mw_size = bar_size - ndev->b2b_off;
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else
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mw_size = bar_size;
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if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
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/* hardware requires that addr is aligned to bar size */
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if (addr & (bar_size - 1))
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return -EINVAL;
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} else {
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if (addr & (PAGE_SIZE - 1))
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return -EINVAL;
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}
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/* make sure the range fits in the usable mw size */
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if (size > mw_size)
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return -EINVAL;
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mmio = ndev->self_mmio;
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xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);
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limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);
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base = pci_resource_start(ndev->ntb.pdev, bar);
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/* Set the limit if supported, if size is not mw_size */
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if (limit_reg && size != mw_size) {
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limit = base + size;
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base_idx = __ilog2_u64(size);
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} else {
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limit = base + mw_size;
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base_idx = __ilog2_u64(mw_size);
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}
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/* set and verify setting the translation address */
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iowrite64(addr, mmio + xlat_reg);
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reg_val = ioread64(mmio + xlat_reg);
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if (reg_val != addr) {
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iowrite64(0, mmio + xlat_reg);
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return -EIO;
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}
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dev_dbg(&ntb->pdev->dev, "BAR %d IMXBASE: %#Lx\n", bar, reg_val);
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/* set and verify setting the limit */
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iowrite64(limit, mmio + limit_reg);
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reg_val = ioread64(mmio + limit_reg);
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if (reg_val != limit) {
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iowrite64(base, mmio + limit_reg);
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iowrite64(0, mmio + xlat_reg);
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return -EIO;
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}
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dev_dbg(&ntb->pdev->dev, "BAR %d IMXLMT: %#Lx\n", bar, reg_val);
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if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
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idx_reg = ndev->xlat_reg->bar2_idx + (idx * 0x2);
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iowrite16(base_idx, mmio + idx_reg);
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reg_val16 = ioread16(mmio + idx_reg);
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if (reg_val16 != base_idx) {
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iowrite64(base, mmio + limit_reg);
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iowrite64(0, mmio + xlat_reg);
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iowrite16(0, mmio + idx_reg);
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return -EIO;
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}
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dev_dbg(&ntb->pdev->dev, "BAR %d IMBASEIDX: %#x\n", bar, reg_val16);
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}
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return 0;
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}
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static int intel_ntb4_link_enable(struct ntb_dev *ntb,
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enum ntb_speed max_speed, enum ntb_width max_width)
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{
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struct intel_ntb_dev *ndev;
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u32 ntb_ctl, ppd0;
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u16 lnkctl;
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ndev = container_of(ntb, struct intel_ntb_dev, ntb);
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dev_dbg(&ntb->pdev->dev,
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"Enabling link with max_speed %d max_width %d\n",
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max_speed, max_width);
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if (max_speed != NTB_SPEED_AUTO)
|
|
dev_dbg(&ntb->pdev->dev,
|
|
"ignoring max_speed %d\n", max_speed);
|
|
if (max_width != NTB_WIDTH_AUTO)
|
|
dev_dbg(&ntb->pdev->dev,
|
|
"ignoring max_width %d\n", max_width);
|
|
|
|
if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD)) {
|
|
u32 ltr;
|
|
|
|
/* Setup active snoop LTR values */
|
|
ltr = NTB_LTR_ACTIVE_REQMNT | NTB_LTR_ACTIVE_VAL | NTB_LTR_ACTIVE_LATSCALE;
|
|
/* Setup active non-snoop values */
|
|
ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
|
|
iowrite32(ltr, ndev->self_mmio + GEN4_LTR_ACTIVE_OFFSET);
|
|
|
|
/* Setup idle snoop LTR values */
|
|
ltr = NTB_LTR_IDLE_VAL | NTB_LTR_IDLE_LATSCALE | NTB_LTR_IDLE_REQMNT;
|
|
/* Setup idle non-snoop values */
|
|
ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
|
|
iowrite32(ltr, ndev->self_mmio + GEN4_LTR_IDLE_OFFSET);
|
|
|
|
/* setup PCIe LTR to active */
|
|
iowrite8(NTB_LTR_SWSEL_ACTIVE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
|
|
}
|
|
|
|
ntb_ctl = NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP;
|
|
ntb_ctl |= NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP;
|
|
iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
|
|
|
|
lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
|
|
lnkctl &= ~GEN4_LINK_CTRL_LINK_DISABLE;
|
|
iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
|
|
|
|
/* start link training in PPD0 */
|
|
ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);
|
|
ppd0 |= GEN4_PPD_LINKTRN;
|
|
iowrite32(ppd0, ndev->self_mmio + GEN4_PPD0_OFFSET);
|
|
|
|
/* make sure link training has started */
|
|
ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);
|
|
if (!(ppd0 & GEN4_PPD_LINKTRN)) {
|
|
dev_warn(&ntb->pdev->dev, "Link is not training\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
ndev->dev_up = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_ntb4_link_disable(struct ntb_dev *ntb)
|
|
{
|
|
struct intel_ntb_dev *ndev;
|
|
u32 ntb_cntl;
|
|
u16 lnkctl;
|
|
|
|
ndev = container_of(ntb, struct intel_ntb_dev, ntb);
|
|
|
|
dev_dbg(&ntb->pdev->dev, "Disabling link\n");
|
|
|
|
/* clear the snoop bits */
|
|
ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
|
|
ntb_cntl &= ~(NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP);
|
|
ntb_cntl &= ~(NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP);
|
|
iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl);
|
|
|
|
lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
|
|
lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
|
|
iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
|
|
|
|
/* set LTR to idle */
|
|
if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD))
|
|
iowrite8(NTB_LTR_SWSEL_IDLE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
|
|
|
|
ndev->dev_up = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_ntb4_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
|
|
resource_size_t *addr_align,
|
|
resource_size_t *size_align,
|
|
resource_size_t *size_max)
|
|
{
|
|
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
|
|
resource_size_t bar_size, mw_size;
|
|
int bar;
|
|
|
|
if (pidx != NTB_DEF_PEER_IDX)
|
|
return -EINVAL;
|
|
|
|
if (idx >= ndev->b2b_idx && !ndev->b2b_off)
|
|
idx += 1;
|
|
|
|
bar = ndev_mw_to_bar(ndev, idx);
|
|
if (bar < 0)
|
|
return bar;
|
|
|
|
bar_size = pci_resource_len(ndev->ntb.pdev, bar);
|
|
|
|
if (idx == ndev->b2b_idx)
|
|
mw_size = bar_size - ndev->b2b_off;
|
|
else
|
|
mw_size = bar_size;
|
|
|
|
if (addr_align) {
|
|
if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN)
|
|
*addr_align = pci_resource_len(ndev->ntb.pdev, bar);
|
|
else
|
|
*addr_align = PAGE_SIZE;
|
|
}
|
|
|
|
if (size_align)
|
|
*size_align = 1;
|
|
|
|
if (size_max)
|
|
*size_max = mw_size;
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct ntb_dev_ops intel_ntb4_ops = {
|
|
.mw_count = intel_ntb_mw_count,
|
|
.mw_get_align = intel_ntb4_mw_get_align,
|
|
.mw_set_trans = intel_ntb4_mw_set_trans,
|
|
.peer_mw_count = intel_ntb_peer_mw_count,
|
|
.peer_mw_get_addr = intel_ntb_peer_mw_get_addr,
|
|
.link_is_up = intel_ntb_link_is_up,
|
|
.link_enable = intel_ntb4_link_enable,
|
|
.link_disable = intel_ntb4_link_disable,
|
|
.db_valid_mask = intel_ntb_db_valid_mask,
|
|
.db_vector_count = intel_ntb_db_vector_count,
|
|
.db_vector_mask = intel_ntb_db_vector_mask,
|
|
.db_read = intel_ntb3_db_read,
|
|
.db_clear = intel_ntb3_db_clear,
|
|
.db_set_mask = intel_ntb_db_set_mask,
|
|
.db_clear_mask = intel_ntb_db_clear_mask,
|
|
.peer_db_addr = intel_ntb3_peer_db_addr,
|
|
.peer_db_set = intel_ntb3_peer_db_set,
|
|
.spad_is_unsafe = intel_ntb_spad_is_unsafe,
|
|
.spad_count = intel_ntb_spad_count,
|
|
.spad_read = intel_ntb_spad_read,
|
|
.spad_write = intel_ntb_spad_write,
|
|
.peer_spad_addr = intel_ntb_peer_spad_addr,
|
|
.peer_spad_read = intel_ntb_peer_spad_read,
|
|
.peer_spad_write = intel_ntb_peer_spad_write,
|
|
};
|
|
|