819 lines
26 KiB
C
819 lines
26 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DRIVERS_PCI_H
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#define DRIVERS_PCI_H
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#include <linux/pci.h>
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/* Number of possible devfns: 0.0 to 1f.7 inclusive */
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#define MAX_NR_DEVFNS 256
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#define PCI_FIND_CAP_TTL 48
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#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
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extern const unsigned char pcie_link_speed[];
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extern bool pci_early_dump;
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bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
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bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
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bool pcie_cap_has_rtctl(const struct pci_dev *dev);
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/* Functions internal to the PCI core code */
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int pci_create_sysfs_dev_files(struct pci_dev *pdev);
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void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
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void pci_cleanup_rom(struct pci_dev *dev);
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#ifdef CONFIG_DMI
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extern const struct attribute_group pci_dev_smbios_attr_group;
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#endif
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enum pci_mmap_api {
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PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
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PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
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};
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int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
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enum pci_mmap_api mmap_api);
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bool pci_reset_supported(struct pci_dev *dev);
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void pci_init_reset_methods(struct pci_dev *dev);
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int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
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int pci_bus_error_reset(struct pci_dev *dev);
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struct pci_cap_saved_data {
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u16 cap_nr;
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bool cap_extended;
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unsigned int size;
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u32 data[];
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};
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struct pci_cap_saved_state {
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struct hlist_node next;
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struct pci_cap_saved_data cap;
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};
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void pci_allocate_cap_save_buffers(struct pci_dev *dev);
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void pci_free_cap_save_buffers(struct pci_dev *dev);
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int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
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int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
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u16 cap, unsigned int size);
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struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
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struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
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u16 cap);
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#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
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#define PCI_PM_D3HOT_WAIT 10 /* msec */
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#define PCI_PM_D3COLD_WAIT 100 /* msec */
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/*
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* Following exit from Conventional Reset, devices must be ready within 1 sec
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* (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
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* Reset (PCIe r6.0 sec 5.8).
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*/
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#define PCI_RESET_WAIT 1000 /* msec */
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/*
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* Devices may extend the 1 sec period through Request Retry Status completions
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* (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec
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* ought to be enough for any device to become responsive.
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*/
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#define PCIE_RESET_READY_POLL_MS 60000 /* msec */
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void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
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void pci_refresh_power_state(struct pci_dev *dev);
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int pci_power_up(struct pci_dev *dev);
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void pci_disable_enabled_device(struct pci_dev *dev);
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int pci_finish_runtime_suspend(struct pci_dev *dev);
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void pcie_clear_device_status(struct pci_dev *dev);
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void pcie_clear_root_pme_status(struct pci_dev *dev);
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bool pci_check_pme_status(struct pci_dev *dev);
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void pci_pme_wakeup_bus(struct pci_bus *bus);
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int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
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void pci_pme_restore(struct pci_dev *dev);
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bool pci_dev_need_resume(struct pci_dev *dev);
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void pci_dev_adjust_pme(struct pci_dev *dev);
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void pci_dev_complete_resume(struct pci_dev *pci_dev);
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void pci_config_pm_runtime_get(struct pci_dev *dev);
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void pci_config_pm_runtime_put(struct pci_dev *dev);
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void pci_pm_init(struct pci_dev *dev);
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void pci_ea_init(struct pci_dev *dev);
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void pci_msi_init(struct pci_dev *dev);
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void pci_msix_init(struct pci_dev *dev);
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bool pci_bridge_d3_possible(struct pci_dev *dev);
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void pci_bridge_d3_update(struct pci_dev *dev);
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void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
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int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
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int timeout);
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static inline void pci_wakeup_event(struct pci_dev *dev)
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{
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/* Wait 100 ms before the system can be put into a sleep state. */
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pm_wakeup_event(&dev->dev, 100);
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}
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static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
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{
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return !!(pci_dev->subordinate);
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}
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static inline bool pci_power_manageable(struct pci_dev *pci_dev)
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{
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/*
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* Currently we allow normal PCI devices and PCI bridges transition
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* into D3 if their bridge_d3 is set.
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*/
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return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
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}
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static inline bool pcie_downstream_port(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_DOWNSTREAM ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE;
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}
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void pci_vpd_init(struct pci_dev *dev);
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void pci_vpd_release(struct pci_dev *dev);
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extern const struct attribute_group pci_dev_vpd_attr_group;
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/* PCI Virtual Channel */
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int pci_save_vc_state(struct pci_dev *dev);
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void pci_restore_vc_state(struct pci_dev *dev);
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void pci_allocate_vc_save_buffers(struct pci_dev *dev);
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/* PCI /proc functions */
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#ifdef CONFIG_PROC_FS
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int pci_proc_attach_device(struct pci_dev *dev);
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int pci_proc_detach_device(struct pci_dev *dev);
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int pci_proc_detach_bus(struct pci_bus *bus);
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#else
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static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
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#endif
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/* Functions for PCI Hotplug drivers to use */
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int pci_hp_add_bridge(struct pci_dev *dev);
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#ifdef HAVE_PCI_LEGACY
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void pci_create_legacy_files(struct pci_bus *bus);
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void pci_remove_legacy_files(struct pci_bus *bus);
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#else
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static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
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static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
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#endif
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/* Lock for read/write access to pci device and bus lists */
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extern struct rw_semaphore pci_bus_sem;
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extern struct mutex pci_slot_mutex;
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extern raw_spinlock_t pci_lock;
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extern unsigned int pci_pm_d3hot_delay;
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#ifdef CONFIG_PCI_MSI
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void pci_no_msi(void);
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#else
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static inline void pci_no_msi(void) { }
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#endif
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void pci_realloc_get_opt(char *);
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static inline int pci_no_d1d2(struct pci_dev *dev)
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{
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unsigned int parent_dstates = 0;
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if (dev->bus->self)
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parent_dstates = dev->bus->self->no_d1d2;
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return (dev->no_d1d2 || parent_dstates);
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}
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extern const struct attribute_group *pci_dev_groups[];
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extern const struct attribute_group *pcibus_groups[];
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extern const struct device_type pci_dev_type;
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extern const struct attribute_group *pci_bus_groups[];
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extern unsigned long pci_hotplug_io_size;
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extern unsigned long pci_hotplug_mmio_size;
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extern unsigned long pci_hotplug_mmio_pref_size;
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extern unsigned long pci_hotplug_bus_size;
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/**
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* pci_match_one_device - Tell if a PCI device structure has a matching
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* PCI device id structure
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* @id: single PCI device id structure to match
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* @dev: the PCI device structure to match against
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*
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* Returns the matching pci_device_id structure or %NULL if there is no match.
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*/
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static inline const struct pci_device_id *
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pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
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{
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if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
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(id->device == PCI_ANY_ID || id->device == dev->device) &&
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(id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
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(id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
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!((id->class ^ dev->class) & id->class_mask))
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return id;
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return NULL;
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}
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/* PCI slot sysfs helper code */
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#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
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extern struct kset *pci_slots_kset;
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struct pci_slot_attribute {
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struct attribute attr;
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ssize_t (*show)(struct pci_slot *, char *);
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ssize_t (*store)(struct pci_slot *, const char *, size_t);
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};
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#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
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enum pci_bar_type {
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pci_bar_unknown, /* Standard PCI BAR probe */
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pci_bar_io, /* An I/O port BAR */
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pci_bar_mem32, /* A 32-bit memory BAR */
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pci_bar_mem64, /* A 64-bit memory BAR */
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};
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struct device *pci_get_host_bridge_device(struct pci_dev *dev);
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void pci_put_host_bridge_device(struct device *dev);
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
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int pci_setup_device(struct pci_dev *dev);
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int reg);
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void pci_configure_ari(struct pci_dev *dev);
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void __pci_bus_size_bridges(struct pci_bus *bus,
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struct list_head *realloc_head);
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void __pci_bus_assign_resources(const struct pci_bus *bus,
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struct list_head *realloc_head,
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struct list_head *fail_head);
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bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
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void pci_reassigndev_resource_alignment(struct pci_dev *dev);
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void pci_disable_bridge_window(struct pci_dev *dev);
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struct pci_bus *pci_bus_get(struct pci_bus *bus);
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void pci_bus_put(struct pci_bus *bus);
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/* PCIe link information from Link Capabilities 2 */
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#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
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((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
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PCI_SPEED_UNKNOWN)
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/* PCIe speed to Mb/s reduced by encoding overhead */
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#define PCIE_SPEED2MBS_ENC(speed) \
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((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
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(speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
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(speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
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(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
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(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
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(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
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0)
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const char *pci_speed_string(enum pci_bus_speed speed);
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enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
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enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
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u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
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void pcie_report_downtraining(struct pci_dev *dev);
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void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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int pos; /* Capability position */
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int nres; /* Number of resources */
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u32 cap; /* SR-IOV Capabilities */
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u16 ctrl; /* SR-IOV Control */
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u16 total_VFs; /* Total VFs associated with the PF */
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u16 initial_VFs; /* Initial VFs associated with the PF */
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u16 num_VFs; /* Number of VFs available */
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u16 offset; /* First VF Routing ID offset */
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u16 stride; /* Following VF stride */
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u16 vf_device; /* VF device ID */
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u32 pgsz; /* Page size for BAR alignment */
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u8 link; /* Function Dependency Link */
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u8 max_VF_buses; /* Max buses consumed by VFs */
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u16 driver_max_VFs; /* Max num VFs driver supports */
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struct pci_dev *dev; /* Lowest numbered PF */
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struct pci_dev *self; /* This PF */
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u32 class; /* VF device */
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u8 hdr_type; /* VF header type */
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u16 subsystem_vendor; /* VF subsystem vendor */
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u16 subsystem_device; /* VF subsystem device */
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resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
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bool drivers_autoprobe; /* Auto probing of VFs by driver */
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};
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/**
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* pci_dev_set_io_state - Set the new error state if possible.
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*
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* @dev: PCI device to set new error_state
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* @new: the state we want dev to be in
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*
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* If the device is experiencing perm_failure, it has to remain in that state.
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* Any other transition is allowed.
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*
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* Returns true if state has been changed to the requested state.
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*/
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static inline bool pci_dev_set_io_state(struct pci_dev *dev,
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pci_channel_state_t new)
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{
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pci_channel_state_t old;
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switch (new) {
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case pci_channel_io_perm_failure:
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xchg(&dev->error_state, pci_channel_io_perm_failure);
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return true;
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case pci_channel_io_frozen:
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old = cmpxchg(&dev->error_state, pci_channel_io_normal,
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pci_channel_io_frozen);
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return old != pci_channel_io_perm_failure;
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case pci_channel_io_normal:
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old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
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pci_channel_io_normal);
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return old != pci_channel_io_perm_failure;
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default:
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return false;
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}
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}
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static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
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{
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pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
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return 0;
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}
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static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
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{
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return dev->error_state == pci_channel_io_perm_failure;
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}
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/* pci_dev priv_flags */
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#define PCI_DEV_ADDED 0
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#define PCI_DPC_RECOVERED 1
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#define PCI_DPC_RECOVERING 2
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static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
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{
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assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
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}
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static inline bool pci_dev_is_added(const struct pci_dev *dev)
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{
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return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
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}
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#ifdef CONFIG_PCIEAER
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#include <linux/aer.h>
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#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
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struct aer_err_info {
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struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
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int error_dev_num;
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unsigned int id:16;
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unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
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unsigned int __pad1:5;
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unsigned int multi_error_valid:1;
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unsigned int first_error:5;
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unsigned int __pad2:2;
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unsigned int tlp_header_valid:1;
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unsigned int status; /* COR/UNCOR Error Status */
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unsigned int mask; /* COR/UNCOR Error Mask */
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struct aer_header_log_regs tlp; /* TLP Header */
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};
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int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
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void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
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#endif /* CONFIG_PCIEAER */
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#ifdef CONFIG_PCIEPORTBUS
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/* Cached RCEC Endpoint Association */
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struct rcec_ea {
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u8 nextbusn;
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u8 lastbusn;
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u32 bitmap;
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};
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#endif
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#ifdef CONFIG_PCIE_DPC
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void pci_save_dpc_state(struct pci_dev *dev);
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void pci_restore_dpc_state(struct pci_dev *dev);
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void pci_dpc_init(struct pci_dev *pdev);
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void dpc_process_error(struct pci_dev *pdev);
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pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
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bool pci_dpc_recovered(struct pci_dev *pdev);
|
|
#else
|
|
static inline void pci_save_dpc_state(struct pci_dev *dev) {}
|
|
static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
|
|
static inline void pci_dpc_init(struct pci_dev *pdev) {}
|
|
static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIEPORTBUS
|
|
void pci_rcec_init(struct pci_dev *dev);
|
|
void pci_rcec_exit(struct pci_dev *dev);
|
|
void pcie_link_rcec(struct pci_dev *rcec);
|
|
void pcie_walk_rcec(struct pci_dev *rcec,
|
|
int (*cb)(struct pci_dev *, void *),
|
|
void *userdata);
|
|
#else
|
|
static inline void pci_rcec_init(struct pci_dev *dev) {}
|
|
static inline void pci_rcec_exit(struct pci_dev *dev) {}
|
|
static inline void pcie_link_rcec(struct pci_dev *rcec) {}
|
|
static inline void pcie_walk_rcec(struct pci_dev *rcec,
|
|
int (*cb)(struct pci_dev *, void *),
|
|
void *userdata) {}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_ATS
|
|
/* Address Translation Service */
|
|
void pci_ats_init(struct pci_dev *dev);
|
|
void pci_restore_ats_state(struct pci_dev *dev);
|
|
#else
|
|
static inline void pci_ats_init(struct pci_dev *d) { }
|
|
static inline void pci_restore_ats_state(struct pci_dev *dev) { }
|
|
#endif /* CONFIG_PCI_ATS */
|
|
|
|
#ifdef CONFIG_PCI_PRI
|
|
void pci_pri_init(struct pci_dev *dev);
|
|
void pci_restore_pri_state(struct pci_dev *pdev);
|
|
#else
|
|
static inline void pci_pri_init(struct pci_dev *dev) { }
|
|
static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_PASID
|
|
void pci_pasid_init(struct pci_dev *dev);
|
|
void pci_restore_pasid_state(struct pci_dev *pdev);
|
|
#else
|
|
static inline void pci_pasid_init(struct pci_dev *dev) { }
|
|
static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
int pci_iov_init(struct pci_dev *dev);
|
|
void pci_iov_release(struct pci_dev *dev);
|
|
void pci_iov_remove(struct pci_dev *dev);
|
|
void pci_iov_update_resource(struct pci_dev *dev, int resno);
|
|
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
|
|
void pci_restore_iov_state(struct pci_dev *dev);
|
|
int pci_iov_bus_range(struct pci_bus *bus);
|
|
extern const struct attribute_group sriov_pf_dev_attr_group;
|
|
extern const struct attribute_group sriov_vf_dev_attr_group;
|
|
#else
|
|
static inline int pci_iov_init(struct pci_dev *dev)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline void pci_iov_release(struct pci_dev *dev)
|
|
|
|
{
|
|
}
|
|
static inline void pci_iov_remove(struct pci_dev *dev)
|
|
{
|
|
}
|
|
static inline void pci_restore_iov_state(struct pci_dev *dev)
|
|
{
|
|
}
|
|
static inline int pci_iov_bus_range(struct pci_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_PCI_IOV */
|
|
|
|
#ifdef CONFIG_PCIE_PTM
|
|
void pci_ptm_init(struct pci_dev *dev);
|
|
void pci_save_ptm_state(struct pci_dev *dev);
|
|
void pci_restore_ptm_state(struct pci_dev *dev);
|
|
void pci_suspend_ptm(struct pci_dev *dev);
|
|
void pci_resume_ptm(struct pci_dev *dev);
|
|
#else
|
|
static inline void pci_ptm_init(struct pci_dev *dev) { }
|
|
static inline void pci_save_ptm_state(struct pci_dev *dev) { }
|
|
static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
|
|
static inline void pci_suspend_ptm(struct pci_dev *dev) { }
|
|
static inline void pci_resume_ptm(struct pci_dev *dev) { }
|
|
#endif
|
|
|
|
unsigned long pci_cardbus_resource_alignment(struct resource *);
|
|
|
|
static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
|
|
struct resource *res)
|
|
{
|
|
#ifdef CONFIG_PCI_IOV
|
|
int resno = res - dev->resource;
|
|
|
|
if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
|
|
return pci_sriov_resource_alignment(dev, resno);
|
|
#endif
|
|
if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
|
|
return pci_cardbus_resource_alignment(res);
|
|
return resource_alignment(res);
|
|
}
|
|
|
|
void pci_acs_init(struct pci_dev *dev);
|
|
#ifdef CONFIG_PCI_QUIRKS
|
|
int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
|
|
int pci_dev_specific_enable_acs(struct pci_dev *dev);
|
|
int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
|
|
#else
|
|
static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
|
|
u16 acs_flags)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
#endif
|
|
|
|
/* PCI error reporting and recovery */
|
|
pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
|
|
pci_channel_state_t state,
|
|
pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
|
|
|
|
bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
|
|
#ifdef CONFIG_PCIEASPM
|
|
void pcie_aspm_init_link_state(struct pci_dev *pdev);
|
|
void pcie_aspm_exit_link_state(struct pci_dev *pdev);
|
|
void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
|
|
#else
|
|
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
|
|
static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
|
|
static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE_ECRC
|
|
void pcie_set_ecrc_checking(struct pci_dev *dev);
|
|
void pcie_ecrc_get_policy(char *str);
|
|
#else
|
|
static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
|
|
static inline void pcie_ecrc_get_policy(char *str) { }
|
|
#endif
|
|
|
|
struct pci_dev_reset_methods {
|
|
u16 vendor;
|
|
u16 device;
|
|
int (*reset)(struct pci_dev *dev, bool probe);
|
|
};
|
|
|
|
struct pci_reset_fn_method {
|
|
int (*reset_fn)(struct pci_dev *pdev, bool probe);
|
|
char *name;
|
|
};
|
|
|
|
#ifdef CONFIG_PCI_QUIRKS
|
|
int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
|
|
#else
|
|
static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
|
|
int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
|
|
struct resource *res);
|
|
#else
|
|
static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
|
|
u16 segment, struct resource *res)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
#endif
|
|
|
|
int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
|
|
int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
|
|
static inline u64 pci_rebar_size_to_bytes(int size)
|
|
{
|
|
return 1ULL << (size + 20);
|
|
}
|
|
|
|
struct device_node;
|
|
|
|
#ifdef CONFIG_OF
|
|
int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
|
|
int of_get_pci_domain_nr(struct device_node *node);
|
|
int of_pci_get_max_link_speed(struct device_node *node);
|
|
u32 of_pci_get_slot_power_limit(struct device_node *node,
|
|
u8 *slot_power_limit_value,
|
|
u8 *slot_power_limit_scale);
|
|
int pci_set_of_node(struct pci_dev *dev);
|
|
void pci_release_of_node(struct pci_dev *dev);
|
|
void pci_set_bus_of_node(struct pci_bus *bus);
|
|
void pci_release_bus_of_node(struct pci_bus *bus);
|
|
|
|
int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
|
|
|
|
#else
|
|
static inline int
|
|
of_pci_parse_bus_range(struct device_node *node, struct resource *res)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static inline int
|
|
of_get_pci_domain_nr(struct device_node *node)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
static inline int
|
|
of_pci_get_max_link_speed(struct device_node *node)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static inline u32
|
|
of_pci_get_slot_power_limit(struct device_node *node,
|
|
u8 *slot_power_limit_value,
|
|
u8 *slot_power_limit_scale)
|
|
{
|
|
if (slot_power_limit_value)
|
|
*slot_power_limit_value = 0;
|
|
if (slot_power_limit_scale)
|
|
*slot_power_limit_scale = 0;
|
|
return 0;
|
|
}
|
|
|
|
static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
|
|
static inline void pci_release_of_node(struct pci_dev *dev) { }
|
|
static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
|
|
static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
|
|
|
|
static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_OF */
|
|
|
|
#ifdef CONFIG_PCIEAER
|
|
void pci_no_aer(void);
|
|
void pci_aer_init(struct pci_dev *dev);
|
|
void pci_aer_exit(struct pci_dev *dev);
|
|
extern const struct attribute_group aer_stats_attr_group;
|
|
void pci_aer_clear_fatal_status(struct pci_dev *dev);
|
|
int pci_aer_clear_status(struct pci_dev *dev);
|
|
int pci_aer_raw_clear_status(struct pci_dev *dev);
|
|
#else
|
|
static inline void pci_no_aer(void) { }
|
|
static inline void pci_aer_init(struct pci_dev *d) { }
|
|
static inline void pci_aer_exit(struct pci_dev *d) { }
|
|
static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
|
|
static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
|
|
static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
|
|
#endif
|
|
|
|
#ifdef CONFIG_ACPI
|
|
int pci_acpi_program_hp_params(struct pci_dev *dev);
|
|
extern const struct attribute_group pci_dev_acpi_attr_group;
|
|
void pci_set_acpi_fwnode(struct pci_dev *dev);
|
|
int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
|
|
bool acpi_pci_power_manageable(struct pci_dev *dev);
|
|
bool acpi_pci_bridge_d3(struct pci_dev *dev);
|
|
int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
|
|
pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
|
|
void acpi_pci_refresh_power_state(struct pci_dev *dev);
|
|
int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
|
|
bool acpi_pci_need_resume(struct pci_dev *dev);
|
|
pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
|
|
#else
|
|
static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
|
|
static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
|
|
{
|
|
return false;
|
|
}
|
|
static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
|
|
{
|
|
return false;
|
|
}
|
|
static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
|
|
{
|
|
return PCI_UNKNOWN;
|
|
}
|
|
static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
|
|
static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline bool acpi_pci_need_resume(struct pci_dev *dev)
|
|
{
|
|
return false;
|
|
}
|
|
static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
|
|
{
|
|
return PCI_POWER_ERROR;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIEASPM
|
|
extern const struct attribute_group aspm_ctrl_attr_group;
|
|
#endif
|
|
|
|
extern const struct attribute_group pci_dev_reset_method_attr_group;
|
|
|
|
#ifdef CONFIG_X86_INTEL_MID
|
|
bool pci_use_mid_pm(void);
|
|
int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
|
|
pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
|
|
#else
|
|
static inline bool pci_use_mid_pm(void)
|
|
{
|
|
return false;
|
|
}
|
|
static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
|
|
{
|
|
return PCI_UNKNOWN;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Config Address for PCI Configuration Mechanism #1
|
|
*
|
|
* See PCI Local Bus Specification, Revision 3.0,
|
|
* Section 3.2.2.3.2, Figure 3-2, p. 50.
|
|
*/
|
|
|
|
#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
|
|
#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
|
|
#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
|
|
|
|
#define PCI_CONF1_BUS_MASK 0xff
|
|
#define PCI_CONF1_DEV_MASK 0x1f
|
|
#define PCI_CONF1_FUNC_MASK 0x7
|
|
#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
|
|
|
|
#define PCI_CONF1_ENABLE BIT(31)
|
|
#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
|
|
#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
|
|
#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
|
|
#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
|
|
|
|
#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
|
|
(PCI_CONF1_ENABLE | \
|
|
PCI_CONF1_BUS(bus) | \
|
|
PCI_CONF1_DEV(dev) | \
|
|
PCI_CONF1_FUNC(func) | \
|
|
PCI_CONF1_REG(reg))
|
|
|
|
/*
|
|
* Extension of PCI Config Address for accessing extended PCIe registers
|
|
*
|
|
* No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
|
|
* or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
|
|
* are used for specifying additional 4 high bits of PCI Express register.
|
|
*/
|
|
|
|
#define PCI_CONF1_EXT_REG_SHIFT 16
|
|
#define PCI_CONF1_EXT_REG_MASK 0xf00
|
|
#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
|
|
|
|
#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
|
|
(PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
|
|
PCI_CONF1_EXT_REG(reg))
|
|
|
|
#endif /* DRIVERS_PCI_H */
|