679 lines
15 KiB
C
679 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for Intel I82092AA PCI-PCMCIA bridge.
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*
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* (C) 2001 Red Hat, Inc.
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*
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* Author: Arjan Van De Ven <arjanv@redhat.com>
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* Loosly based on i82365.c from the pcmcia-cs package
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <pcmcia/ss.h>
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#include <linux/io.h>
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#include "i82092aa.h"
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#include "i82365.h"
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MODULE_LICENSE("GPL");
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/* PCI core routines */
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static const struct pci_device_id i82092aa_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
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static struct pci_driver i82092aa_pci_driver = {
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.name = "i82092aa",
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.id_table = i82092aa_pci_ids,
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.probe = i82092aa_pci_probe,
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.remove = i82092aa_pci_remove,
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};
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/* the pccard structure and its functions */
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static struct pccard_operations i82092aa_operations = {
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.init = i82092aa_init,
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.get_status = i82092aa_get_status,
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.set_socket = i82092aa_set_socket,
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.set_io_map = i82092aa_set_io_map,
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.set_mem_map = i82092aa_set_mem_map,
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};
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/* The card can do up to 4 sockets, allocate a structure for each of them */
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struct socket_info {
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int number;
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int card_state;
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/* 0 = no socket,
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* 1 = empty socket,
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* 2 = card but not initialized,
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* 3 = operational card
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*/
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unsigned int io_base; /* base io address of the socket */
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struct pcmcia_socket socket;
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struct pci_dev *dev; /* The PCI device for the socket */
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};
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#define MAX_SOCKETS 4
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static struct socket_info sockets[MAX_SOCKETS];
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static int socket_count; /* shortcut */
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static int i82092aa_pci_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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unsigned char configbyte;
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int i, ret;
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ret = pci_enable_device(dev);
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if (ret)
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return ret;
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/* PCI Configuration Control */
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pci_read_config_byte(dev, 0x40, &configbyte);
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switch (configbyte&6) {
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case 0:
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socket_count = 2;
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break;
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case 2:
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socket_count = 1;
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break;
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case 4:
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case 6:
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socket_count = 4;
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break;
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default:
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dev_err(&dev->dev,
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"Oops, you did something we didn't think of.\n");
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ret = -EIO;
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goto err_out_disable;
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}
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dev_info(&dev->dev, "configured as a %d socket device.\n",
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socket_count);
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if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
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ret = -EBUSY;
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goto err_out_disable;
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}
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for (i = 0; i < socket_count; i++) {
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sockets[i].card_state = 1; /* 1 = present but empty */
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sockets[i].io_base = pci_resource_start(dev, 0);
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sockets[i].dev = dev;
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sockets[i].socket.features |= SS_CAP_PCCARD;
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sockets[i].socket.map_size = 0x1000;
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sockets[i].socket.irq_mask = 0;
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sockets[i].socket.pci_irq = dev->irq;
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sockets[i].socket.cb_dev = dev;
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sockets[i].socket.owner = THIS_MODULE;
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sockets[i].number = i;
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if (card_present(i)) {
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sockets[i].card_state = 3;
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dev_dbg(&dev->dev, "slot %i is occupied\n", i);
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} else {
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dev_dbg(&dev->dev, "slot %i is vacant\n", i);
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}
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}
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/* Now, specifiy that all interrupts are to be done as PCI interrupts
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* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt
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*/
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configbyte = 0xFF;
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/* PCI Interrupt Routing Register */
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pci_write_config_byte(dev, 0x50, configbyte);
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/* Register the interrupt handler */
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dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq);
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ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED,
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"i82092aa", i82092aa_interrupt);
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if (ret) {
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dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n",
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dev->irq);
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goto err_out_free_res;
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}
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for (i = 0; i < socket_count; i++) {
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sockets[i].socket.dev.parent = &dev->dev;
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sockets[i].socket.ops = &i82092aa_operations;
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sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
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ret = pcmcia_register_socket(&sockets[i].socket);
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if (ret)
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goto err_out_free_sockets;
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}
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return 0;
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err_out_free_sockets:
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if (i) {
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for (i--; i >= 0; i--)
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pcmcia_unregister_socket(&sockets[i].socket);
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}
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free_irq(dev->irq, i82092aa_interrupt);
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err_out_free_res:
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release_region(pci_resource_start(dev, 0), 2);
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err_out_disable:
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pci_disable_device(dev);
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return ret;
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}
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static void i82092aa_pci_remove(struct pci_dev *dev)
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{
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int i;
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free_irq(dev->irq, i82092aa_interrupt);
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for (i = 0; i < socket_count; i++)
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pcmcia_unregister_socket(&sockets[i].socket);
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}
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static DEFINE_SPINLOCK(port_lock);
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/* basic value read/write functions */
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static unsigned char indirect_read(int socket, unsigned short reg)
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{
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unsigned short int port;
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unsigned char val;
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unsigned long flags;
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spin_lock_irqsave(&port_lock, flags);
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reg += socket * 0x40;
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port = sockets[socket].io_base;
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outb(reg, port);
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val = inb(port+1);
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spin_unlock_irqrestore(&port_lock, flags);
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return val;
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}
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static void indirect_write(int socket, unsigned short reg, unsigned char value)
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{
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unsigned short int port;
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unsigned long flags;
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spin_lock_irqsave(&port_lock, flags);
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reg = reg + socket * 0x40;
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port = sockets[socket].io_base;
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outb(reg, port);
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outb(value, port+1);
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spin_unlock_irqrestore(&port_lock, flags);
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}
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static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
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{
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unsigned short int port;
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unsigned char val;
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unsigned long flags;
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spin_lock_irqsave(&port_lock, flags);
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reg = reg + socket * 0x40;
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port = sockets[socket].io_base;
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outb(reg, port);
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val = inb(port+1);
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val |= mask;
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outb(reg, port);
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outb(val, port+1);
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spin_unlock_irqrestore(&port_lock, flags);
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}
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static void indirect_resetbit(int socket,
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unsigned short reg, unsigned char mask)
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{
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unsigned short int port;
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unsigned char val;
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unsigned long flags;
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spin_lock_irqsave(&port_lock, flags);
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reg = reg + socket * 0x40;
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port = sockets[socket].io_base;
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outb(reg, port);
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val = inb(port+1);
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val &= ~mask;
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outb(reg, port);
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outb(val, port+1);
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spin_unlock_irqrestore(&port_lock, flags);
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}
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static void indirect_write16(int socket,
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unsigned short reg, unsigned short value)
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{
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unsigned short int port;
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unsigned char val;
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unsigned long flags;
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spin_lock_irqsave(&port_lock, flags);
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reg = reg + socket * 0x40;
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port = sockets[socket].io_base;
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outb(reg, port);
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val = value & 255;
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outb(val, port+1);
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reg++;
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outb(reg, port);
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val = value>>8;
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outb(val, port+1);
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spin_unlock_irqrestore(&port_lock, flags);
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}
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/* simple helper functions */
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/* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
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static int cycle_time = 120;
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static int to_cycles(int ns)
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{
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if (cycle_time != 0)
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return ns/cycle_time;
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else
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return 0;
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}
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/* Interrupt handler functionality */
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static irqreturn_t i82092aa_interrupt(int irq, void *dev)
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{
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int i;
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int loopcount = 0;
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int handled = 0;
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unsigned int events, active = 0;
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while (1) {
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loopcount++;
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if (loopcount > 20) {
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pr_err("i82092aa: infinite eventloop in interrupt\n");
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break;
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}
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active = 0;
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for (i = 0; i < socket_count; i++) {
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int csc;
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/* Inactive socket, should not happen */
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if (sockets[i].card_state == 0)
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continue;
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/* card status change register */
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csc = indirect_read(i, I365_CSC);
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if (csc == 0) /* no events on this socket */
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continue;
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handled = 1;
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events = 0;
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if (csc & I365_CSC_DETECT) {
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events |= SS_DETECT;
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dev_info(&sockets[i].dev->dev,
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"Card detected in socket %i!\n", i);
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}
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if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) {
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/* For IO/CARDS, bit 0 means "read the card" */
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if (csc & I365_CSC_STSCHG)
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events |= SS_STSCHG;
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} else {
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/* Check for battery/ready events */
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if (csc & I365_CSC_BVD1)
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events |= SS_BATDEAD;
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if (csc & I365_CSC_BVD2)
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events |= SS_BATWARN;
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if (csc & I365_CSC_READY)
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events |= SS_READY;
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}
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if (events)
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pcmcia_parse_events(&sockets[i].socket, events);
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active |= events;
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}
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if (active == 0) /* no more events to handle */
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break;
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}
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return IRQ_RETVAL(handled);
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}
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/* socket functions */
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static int card_present(int socketno)
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{
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unsigned int val;
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if ((socketno < 0) || (socketno >= MAX_SOCKETS))
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return 0;
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if (sockets[socketno].io_base == 0)
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return 0;
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val = indirect_read(socketno, 1); /* Interface status register */
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if ((val&12) == 12)
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return 1;
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return 0;
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}
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static void set_bridge_state(int sock)
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{
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indirect_write(sock, I365_GBLCTL, 0x00);
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indirect_write(sock, I365_GENCTL, 0x00);
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indirect_setbit(sock, I365_INTCTL, 0x08);
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}
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static int i82092aa_init(struct pcmcia_socket *sock)
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{
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int i;
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struct resource res = { .start = 0, .end = 0x0fff };
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pccard_io_map io = { 0, 0, 0, 0, 1 };
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pccard_mem_map mem = { .res = &res, };
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for (i = 0; i < 2; i++) {
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io.map = i;
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i82092aa_set_io_map(sock, &io);
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}
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for (i = 0; i < 5; i++) {
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mem.map = i;
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i82092aa_set_mem_map(sock, &mem);
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}
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return 0;
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}
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static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
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{
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unsigned int sock = container_of(socket,
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struct socket_info, socket)->number;
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unsigned int status;
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/* Interface Status Register */
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status = indirect_read(sock, I365_STATUS);
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*value = 0;
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if ((status & I365_CS_DETECT) == I365_CS_DETECT)
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*value |= SS_DETECT;
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/* IO cards have a different meaning of bits 0,1 */
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/* Also notice the inverse-logic on the bits */
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if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
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/* IO card */
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if (!(status & I365_CS_STSCHG))
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*value |= SS_STSCHG;
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} else { /* non I/O card */
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if (!(status & I365_CS_BVD1))
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*value |= SS_BATDEAD;
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if (!(status & I365_CS_BVD2))
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*value |= SS_BATWARN;
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}
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if (status & I365_CS_WRPROT)
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(*value) |= SS_WRPROT; /* card is write protected */
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if (status & I365_CS_READY)
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(*value) |= SS_READY; /* card is not busy */
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if (status & I365_CS_POWERON)
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(*value) |= SS_POWERON; /* power is applied to the card */
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return 0;
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}
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static int i82092aa_set_socket(struct pcmcia_socket *socket,
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socket_state_t *state)
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{
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struct socket_info *sock_info = container_of(socket, struct socket_info,
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socket);
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unsigned int sock = sock_info->number;
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unsigned char reg;
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/* First, set the global controller options */
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set_bridge_state(sock);
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/* Values for the IGENC register */
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reg = 0;
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/* The reset bit has "inverse" logic */
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if (!(state->flags & SS_RESET))
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reg = reg | I365_PC_RESET;
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if (state->flags & SS_IOCARD)
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reg = reg | I365_PC_IOCARD;
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/* IGENC, Interrupt and General Control Register */
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indirect_write(sock, I365_INTCTL, reg);
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/* Power registers */
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reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
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if (state->flags & SS_PWR_AUTO) {
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dev_info(&sock_info->dev->dev, "Auto power\n");
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reg |= I365_PWR_AUTO; /* automatic power mngmnt */
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}
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if (state->flags & SS_OUTPUT_ENA) {
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dev_info(&sock_info->dev->dev, "Power Enabled\n");
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reg |= I365_PWR_OUT; /* enable power */
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}
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switch (state->Vcc) {
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case 0:
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break;
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case 50:
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dev_info(&sock_info->dev->dev,
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"setting voltage to Vcc to 5V on socket %i\n",
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sock);
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reg |= I365_VCC_5V;
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break;
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default:
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dev_err(&sock_info->dev->dev,
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"%s called with invalid VCC power value: %i",
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__func__, state->Vcc);
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return -EINVAL;
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}
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switch (state->Vpp) {
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case 0:
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dev_info(&sock_info->dev->dev,
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"not setting Vpp on socket %i\n", sock);
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break;
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case 50:
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dev_info(&sock_info->dev->dev,
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"setting Vpp to 5.0 for socket %i\n", sock);
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reg |= I365_VPP1_5V | I365_VPP2_5V;
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break;
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case 120:
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dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n");
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reg |= I365_VPP1_12V | I365_VPP2_12V;
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break;
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default:
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dev_err(&sock_info->dev->dev,
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"%s called with invalid VPP power value: %i",
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__func__, state->Vcc);
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return -EINVAL;
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}
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if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */
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indirect_write(sock, I365_POWER, reg);
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/* Enable specific interrupt events */
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reg = 0x00;
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if (state->csc_mask & SS_DETECT)
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reg |= I365_CSC_DETECT;
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if (state->flags & SS_IOCARD) {
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if (state->csc_mask & SS_STSCHG)
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reg |= I365_CSC_STSCHG;
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} else {
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if (state->csc_mask & SS_BATDEAD)
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reg |= I365_CSC_BVD1;
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if (state->csc_mask & SS_BATWARN)
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reg |= I365_CSC_BVD2;
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if (state->csc_mask & SS_READY)
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reg |= I365_CSC_READY;
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}
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/* now write the value and clear the (probably bogus) pending stuff
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* by doing a dummy read
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*/
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indirect_write(sock, I365_CSCINT, reg);
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(void)indirect_read(sock, I365_CSC);
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return 0;
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}
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static int i82092aa_set_io_map(struct pcmcia_socket *socket,
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struct pccard_io_map *io)
|
|
{
|
|
struct socket_info *sock_info = container_of(socket, struct socket_info,
|
|
socket);
|
|
unsigned int sock = sock_info->number;
|
|
unsigned char map, ioctl;
|
|
|
|
map = io->map;
|
|
|
|
/* Check error conditions */
|
|
if (map > 1)
|
|
return -EINVAL;
|
|
|
|
if ((io->start > 0xffff) || (io->stop > 0xffff)
|
|
|| (io->stop < io->start))
|
|
return -EINVAL;
|
|
|
|
/* Turn off the window before changing anything */
|
|
if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
|
|
indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
|
|
|
|
/* write the new values */
|
|
indirect_write16(sock, I365_IO(map)+I365_W_START, io->start);
|
|
indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop);
|
|
|
|
ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
|
|
|
|
if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
|
|
ioctl |= I365_IOCTL_16BIT(map);
|
|
|
|
indirect_write(sock, I365_IOCTL, ioctl);
|
|
|
|
/* Turn the window back on if needed */
|
|
if (io->flags & MAP_ACTIVE)
|
|
indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i82092aa_set_mem_map(struct pcmcia_socket *socket,
|
|
struct pccard_mem_map *mem)
|
|
{
|
|
struct socket_info *sock_info = container_of(socket, struct socket_info,
|
|
socket);
|
|
unsigned int sock = sock_info->number;
|
|
struct pci_bus_region region;
|
|
unsigned short base, i;
|
|
unsigned char map;
|
|
|
|
pcibios_resource_to_bus(sock_info->dev->bus, ®ion, mem->res);
|
|
|
|
map = mem->map;
|
|
if (map > 4)
|
|
return -EINVAL;
|
|
|
|
if ((mem->card_start > 0x3ffffff) || (region.start > region.end) ||
|
|
(mem->speed > 1000)) {
|
|
dev_err(&sock_info->dev->dev,
|
|
"invalid mem map for socket %i: %llx to %llx with a start of %x\n",
|
|
sock,
|
|
(unsigned long long)region.start,
|
|
(unsigned long long)region.end,
|
|
mem->card_start);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Turn off the window before changing anything */
|
|
if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
|
|
indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
|
|
|
|
/* write the start address */
|
|
base = I365_MEM(map);
|
|
i = (region.start >> 12) & 0x0fff;
|
|
if (mem->flags & MAP_16BIT)
|
|
i |= I365_MEM_16BIT;
|
|
if (mem->flags & MAP_0WS)
|
|
i |= I365_MEM_0WS;
|
|
indirect_write16(sock, base+I365_W_START, i);
|
|
|
|
/* write the stop address */
|
|
|
|
i = (region.end >> 12) & 0x0fff;
|
|
switch (to_cycles(mem->speed)) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
i |= I365_MEM_WS0;
|
|
break;
|
|
case 2:
|
|
i |= I365_MEM_WS1;
|
|
break;
|
|
default:
|
|
i |= I365_MEM_WS1 | I365_MEM_WS0;
|
|
break;
|
|
}
|
|
|
|
indirect_write16(sock, base+I365_W_STOP, i);
|
|
|
|
/* card start */
|
|
|
|
i = ((mem->card_start - region.start) >> 12) & 0x3fff;
|
|
if (mem->flags & MAP_WRPROT)
|
|
i |= I365_MEM_WRPROT;
|
|
if (mem->flags & MAP_ATTRIB)
|
|
i |= I365_MEM_REG;
|
|
indirect_write16(sock, base+I365_W_OFF, i);
|
|
|
|
/* Enable the window if necessary */
|
|
if (mem->flags & MAP_ACTIVE)
|
|
indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init i82092aa_module_init(void)
|
|
{
|
|
return pci_register_driver(&i82092aa_pci_driver);
|
|
}
|
|
|
|
static void __exit i82092aa_module_exit(void)
|
|
{
|
|
pci_unregister_driver(&i82092aa_pci_driver);
|
|
if (sockets[0].io_base > 0)
|
|
release_region(sockets[0].io_base, 2);
|
|
}
|
|
|
|
module_init(i82092aa_module_init);
|
|
module_exit(i82092aa_module_exit);
|
|
|