245 lines
8.2 KiB
C
245 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Marvell Orion pinctrl driver based on mvebu pinctrl core
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*
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* Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* The first 16 MPP pins on Orion are easy to handle: they are
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* configured through 2 consecutive registers, located at the base
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* address of the MPP device.
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*
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* However the last 4 MPP pins are handled by a register at offset
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* 0x50 from the base address, so it is not consecutive with the first
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* two registers.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-mvebu.h"
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static void __iomem *mpp_base;
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static void __iomem *high_mpp_base;
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static int orion_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
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unsigned pid, unsigned long *config)
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{
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unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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if (pid < 16) {
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unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
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}
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else {
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*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
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}
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return 0;
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}
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static int orion_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
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unsigned pid, unsigned long config)
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{
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unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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if (pid < 16) {
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unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
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writel(reg | (config << shift), mpp_base + off);
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}
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else {
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u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
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writel(reg | (config << shift), high_mpp_base);
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}
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return 0;
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}
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#define V(f5181, f5182, f5281) \
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((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
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enum orion_variant {
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V_5181 = V(1, 0, 0),
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V_5182 = V(0, 1, 0),
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V_5281 = V(0, 0, 1),
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V_ALL = V(1, 1, 1),
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};
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static struct mvebu_mpp_mode orion_mpp_modes[] = {
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MPP_MODE(0,
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MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL),
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MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)),
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MPP_MODE(1,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)),
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MPP_MODE(2,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL),
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MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)),
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MPP_MODE(3,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)),
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MPP_MODE(4,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL),
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MPP_VAR_FUNCTION(0x4, "bootnand", "re", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V_5182)),
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MPP_MODE(5,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL),
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MPP_VAR_FUNCTION(0x4, "bootnand", "we", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V_5182)),
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MPP_MODE(6,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
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MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
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MPP_MODE(7,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
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MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
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MPP_MODE(8,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "col", V_ALL)),
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MPP_MODE(9,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "rxerr", V_ALL)),
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MPP_MODE(10,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "crs", V_ALL)),
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MPP_MODE(11,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txerr", V_ALL)),
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MPP_MODE(12,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd4", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "re1", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
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MPP_MODE(13,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "we1", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
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MPP_MODE(14,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd6", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "re2", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata0", "ledact", V_5182)),
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MPP_MODE(15,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd7", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "we2", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata1", "ledact", V_5182)),
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MPP_MODE(16,
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MPP_VAR_FUNCTION(0x0, "uart1", "rxd", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd4", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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MPP_MODE(17,
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MPP_VAR_FUNCTION(0x0, "uart1", "txd", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd5", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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MPP_MODE(18,
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MPP_VAR_FUNCTION(0x0, "uart1", "cts", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd6", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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MPP_MODE(19,
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MPP_VAR_FUNCTION(0x0, "uart1", "rts", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd7", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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};
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static const struct mvebu_mpp_ctrl orion_mpp_controls[] = {
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MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
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};
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static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 16),
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};
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static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 19),
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};
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static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 16),
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};
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static struct mvebu_pinctrl_soc_info mv88f5181_info = {
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.variant = V_5181,
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.controls = orion_mpp_controls,
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.ncontrols = ARRAY_SIZE(orion_mpp_controls),
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.modes = orion_mpp_modes,
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.nmodes = ARRAY_SIZE(orion_mpp_modes),
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.gpioranges = mv88f5181_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
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};
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static struct mvebu_pinctrl_soc_info mv88f5182_info = {
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.variant = V_5182,
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.controls = orion_mpp_controls,
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.ncontrols = ARRAY_SIZE(orion_mpp_controls),
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.modes = orion_mpp_modes,
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.nmodes = ARRAY_SIZE(orion_mpp_modes),
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.gpioranges = mv88f5182_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
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};
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static struct mvebu_pinctrl_soc_info mv88f5281_info = {
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.variant = V_5281,
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.controls = orion_mpp_controls,
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.ncontrols = ARRAY_SIZE(orion_mpp_controls),
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.modes = orion_mpp_modes,
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.nmodes = ARRAY_SIZE(orion_mpp_modes),
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.gpioranges = mv88f5281_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
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};
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/*
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* There are multiple variants of the Orion SoCs, but in terms of pin
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* muxing, they are identical.
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*/
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static const struct of_device_id orion_pinctrl_of_match[] = {
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{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
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{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
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{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
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{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
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{ }
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};
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static int orion_pinctrl_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match =
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of_match_device(orion_pinctrl_of_match, &pdev->dev);
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pdev->dev.platform_data = (void*)match->data;
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mpp_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mpp_base))
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return PTR_ERR(mpp_base);
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high_mpp_base = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(high_mpp_base))
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return PTR_ERR(high_mpp_base);
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return mvebu_pinctrl_probe(pdev);
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}
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static struct platform_driver orion_pinctrl_driver = {
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.driver = {
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.name = "orion-pinctrl",
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.of_match_table = of_match_ptr(orion_pinctrl_of_match),
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},
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.probe = orion_pinctrl_probe,
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};
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builtin_platform_driver(orion_pinctrl_driver);
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