488 lines
11 KiB
C
488 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* arch/powerpc/sysdev/qe_lib/qe_ic.c
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*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Li Yang <leoli@freescale.com>
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* Based on code from Shlomi Gridish <gridish@freescale.com>
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*
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* QUICC ENGINE Interrupt Controller
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*/
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <soc/fsl/qe/qe.h>
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#define NR_QE_IC_INTS 64
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/* QE IC registers offset */
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#define QEIC_CICR 0x00
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#define QEIC_CIVEC 0x04
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#define QEIC_CIPXCC 0x10
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#define QEIC_CIPYCC 0x14
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#define QEIC_CIPWCC 0x18
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#define QEIC_CIPZCC 0x1c
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#define QEIC_CIMR 0x20
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#define QEIC_CRIMR 0x24
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#define QEIC_CIPRTA 0x30
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#define QEIC_CIPRTB 0x34
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#define QEIC_CHIVEC 0x60
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struct qe_ic {
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/* Control registers offset */
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__be32 __iomem *regs;
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/* The remapper for this QEIC */
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struct irq_domain *irqhost;
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/* The "linux" controller struct */
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struct irq_chip hc_irq;
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/* VIRQ numbers of QE high/low irqs */
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int virq_high;
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int virq_low;
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};
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/*
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* QE interrupt controller internal structure
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*/
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struct qe_ic_info {
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/* Location of this source at the QIMR register */
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u32 mask;
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/* Mask register offset */
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u32 mask_reg;
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/*
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* For grouped interrupts sources - the interrupt code as
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* appears at the group priority register
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*/
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u8 pri_code;
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/* Group priority register offset */
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u32 pri_reg;
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};
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static DEFINE_RAW_SPINLOCK(qe_ic_lock);
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static struct qe_ic_info qe_ic_info[] = {
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[1] = {
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.mask = 0x00008000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPWCC,
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},
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[2] = {
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.mask = 0x00004000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPWCC,
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},
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[3] = {
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.mask = 0x00002000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPWCC,
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},
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[10] = {
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.mask = 0x00000040,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPZCC,
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},
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[11] = {
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.mask = 0x00000020,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPZCC,
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},
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[12] = {
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.mask = 0x00000010,
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.mask_reg = QEIC_CIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPZCC,
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},
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[13] = {
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.mask = 0x00000008,
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.mask_reg = QEIC_CIMR,
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.pri_code = 4,
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.pri_reg = QEIC_CIPZCC,
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},
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[14] = {
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.mask = 0x00000004,
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.mask_reg = QEIC_CIMR,
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.pri_code = 5,
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.pri_reg = QEIC_CIPZCC,
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},
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[15] = {
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.mask = 0x00000002,
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.mask_reg = QEIC_CIMR,
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.pri_code = 6,
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.pri_reg = QEIC_CIPZCC,
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},
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[20] = {
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.mask = 0x10000000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPRTA,
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},
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[25] = {
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.mask = 0x00800000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPRTB,
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},
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[26] = {
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.mask = 0x00400000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPRTB,
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},
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[27] = {
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.mask = 0x00200000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPRTB,
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},
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[28] = {
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.mask = 0x00100000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPRTB,
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},
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[32] = {
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.mask = 0x80000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPXCC,
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},
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[33] = {
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.mask = 0x40000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPXCC,
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},
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[34] = {
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.mask = 0x20000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPXCC,
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},
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[35] = {
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.mask = 0x10000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPXCC,
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},
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[36] = {
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.mask = 0x08000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 4,
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.pri_reg = QEIC_CIPXCC,
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},
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[40] = {
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.mask = 0x00800000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPYCC,
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},
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[41] = {
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.mask = 0x00400000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPYCC,
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},
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[42] = {
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.mask = 0x00200000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPYCC,
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},
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[43] = {
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.mask = 0x00100000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPYCC,
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},
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};
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static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
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{
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return ioread32be(base + (reg >> 2));
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}
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static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
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u32 value)
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{
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iowrite32be(value, base + (reg >> 2));
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}
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static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
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{
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return irq_get_chip_data(virq);
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}
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static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
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{
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return irq_data_get_irq_chip_data(d);
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}
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static void qe_ic_unmask_irq(struct irq_data *d)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
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unsigned int src = irqd_to_hwirq(d);
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unsigned long flags;
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u32 temp;
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raw_spin_lock_irqsave(&qe_ic_lock, flags);
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temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
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qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
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temp | qe_ic_info[src].mask);
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raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
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}
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static void qe_ic_mask_irq(struct irq_data *d)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
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unsigned int src = irqd_to_hwirq(d);
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unsigned long flags;
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u32 temp;
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raw_spin_lock_irqsave(&qe_ic_lock, flags);
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temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
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qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
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temp & ~qe_ic_info[src].mask);
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/* Flush the above write before enabling interrupts; otherwise,
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* spurious interrupts will sometimes happen. To be 100% sure
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* that the write has reached the device before interrupts are
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* enabled, the mask register would have to be read back; however,
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* this is not required for correctness, only to avoid wasting
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* time on a large number of spurious interrupts. In testing,
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* a sync reduced the observed spurious interrupts to zero.
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*/
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mb();
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raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
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}
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static struct irq_chip qe_ic_irq_chip = {
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.name = "QEIC",
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.irq_unmask = qe_ic_unmask_irq,
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.irq_mask = qe_ic_mask_irq,
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.irq_mask_ack = qe_ic_mask_irq,
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};
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static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,
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enum irq_domain_bus_token bus_token)
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{
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/* Exact match, unless qe_ic node is NULL */
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struct device_node *of_node = irq_domain_get_of_node(h);
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return of_node == NULL || of_node == node;
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}
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static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct qe_ic *qe_ic = h->host_data;
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struct irq_chip *chip;
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if (hw >= ARRAY_SIZE(qe_ic_info)) {
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pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
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return -EINVAL;
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}
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if (qe_ic_info[hw].mask == 0) {
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printk(KERN_ERR "Can't map reserved IRQ\n");
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return -EINVAL;
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}
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/* Default chip */
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chip = &qe_ic->hc_irq;
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irq_set_chip_data(virq, qe_ic);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops qe_ic_host_ops = {
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.match = qe_ic_host_match,
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.map = qe_ic_host_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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/* Return an interrupt vector or 0 if no interrupt is pending. */
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static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
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{
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int irq;
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BUG_ON(qe_ic == NULL);
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/* get the interrupt source vector. */
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irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
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if (irq == 0)
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return 0;
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return irq_linear_revmap(qe_ic->irqhost, irq);
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}
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/* Return an interrupt vector or 0 if no interrupt is pending. */
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static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
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{
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int irq;
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BUG_ON(qe_ic == NULL);
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/* get the interrupt source vector. */
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irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
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if (irq == 0)
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return 0;
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return irq_linear_revmap(qe_ic->irqhost, irq);
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}
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static void qe_ic_cascade_low(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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if (chip->irq_eoi)
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chip->irq_eoi(&desc->irq_data);
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}
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static void qe_ic_cascade_high(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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if (chip->irq_eoi)
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chip->irq_eoi(&desc->irq_data);
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}
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static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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cascade_irq = qe_ic_get_high_irq(qe_ic);
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if (cascade_irq == 0)
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cascade_irq = qe_ic_get_low_irq(qe_ic);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static int qe_ic_init(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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void (*low_handler)(struct irq_desc *desc);
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void (*high_handler)(struct irq_desc *desc);
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struct qe_ic *qe_ic;
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struct resource *res;
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struct device_node *node = pdev->dev.of_node;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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dev_err(dev, "no memory resource defined\n");
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return -ENODEV;
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}
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qe_ic = devm_kzalloc(dev, sizeof(*qe_ic), GFP_KERNEL);
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if (qe_ic == NULL)
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return -ENOMEM;
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qe_ic->regs = devm_ioremap(dev, res->start, resource_size(res));
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if (qe_ic->regs == NULL) {
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dev_err(dev, "failed to ioremap() registers\n");
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return -ENODEV;
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}
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qe_ic->hc_irq = qe_ic_irq_chip;
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qe_ic->virq_high = platform_get_irq(pdev, 0);
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qe_ic->virq_low = platform_get_irq(pdev, 1);
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if (qe_ic->virq_low <= 0)
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return -ENODEV;
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if (qe_ic->virq_high > 0 && qe_ic->virq_high != qe_ic->virq_low) {
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low_handler = qe_ic_cascade_low;
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high_handler = qe_ic_cascade_high;
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} else {
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low_handler = qe_ic_cascade_muxed_mpic;
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high_handler = NULL;
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}
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qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
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&qe_ic_host_ops, qe_ic);
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if (qe_ic->irqhost == NULL) {
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dev_err(dev, "failed to add irq domain\n");
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return -ENODEV;
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}
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qe_ic_write(qe_ic->regs, QEIC_CICR, 0);
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irq_set_handler_data(qe_ic->virq_low, qe_ic);
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irq_set_chained_handler(qe_ic->virq_low, low_handler);
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if (high_handler) {
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irq_set_handler_data(qe_ic->virq_high, qe_ic);
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irq_set_chained_handler(qe_ic->virq_high, high_handler);
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}
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return 0;
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}
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static const struct of_device_id qe_ic_ids[] = {
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{ .compatible = "fsl,qe-ic"},
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{ .type = "qeic"},
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{},
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};
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static struct platform_driver qe_ic_driver =
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{
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.driver = {
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.name = "qe-ic",
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.of_match_table = qe_ic_ids,
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},
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.probe = qe_ic_init,
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};
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static int __init qe_ic_of_init(void)
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{
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platform_driver_register(&qe_ic_driver);
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return 0;
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}
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subsys_initcall(qe_ic_of_init);
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