470 lines
14 KiB
C
470 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// PCI1xxxx SPI driver
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// Copyright (C) 2022 Microchip Technology Inc.
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// Authors: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
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// Kumaravel Thiagarajan <Kumaravel.Thiagarajan@microchip.com>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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#define DRV_NAME "spi-pci1xxxx"
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#define SYS_FREQ_DEFAULT (62500000)
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#define PCI1XXXX_SPI_MAX_CLOCK_HZ (30000000)
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#define PCI1XXXX_SPI_CLK_20MHZ (20000000)
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#define PCI1XXXX_SPI_CLK_15MHZ (15000000)
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#define PCI1XXXX_SPI_CLK_12MHZ (12000000)
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#define PCI1XXXX_SPI_CLK_10MHZ (10000000)
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#define PCI1XXXX_SPI_MIN_CLOCK_HZ (2000000)
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#define PCI1XXXX_SPI_BUFFER_SIZE (320)
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#define SPI_MST_CTL_DEVSEL_MASK (GENMASK(27, 25))
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#define SPI_MST_CTL_CMD_LEN_MASK (GENMASK(16, 8))
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#define SPI_MST_CTL_SPEED_MASK (GENMASK(7, 5))
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#define SPI_MSI_VECTOR_SEL_MASK (GENMASK(4, 4))
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#define SPI_MST_CTL_FORCE_CE (BIT(4))
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#define SPI_MST_CTL_MODE_SEL (BIT(2))
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#define SPI_MST_CTL_GO (BIT(0))
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#define SPI_MST1_ADDR_BASE (0x800)
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/* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
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#define SPI_MST_CMD_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x00)
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#define SPI_MST_RSP_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x200)
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#define SPI_MST_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x400)
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#define SPI_MST_EVENT_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x420)
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#define SPI_MST_EVENT_MASK_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x424)
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#define SPI_MST_PAD_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x460)
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#define SPIALERT_MST_DB_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x464)
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#define SPIALERT_MST_VAL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x468)
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#define SPI_PCI_CTRL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x480)
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#define PCI1XXXX_IRQ_FLAGS (IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE)
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#define SPI_MAX_DATA_LEN 320
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#define PCI1XXXX_SPI_TIMEOUT (msecs_to_jiffies(100))
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#define SPI_INTR BIT(8)
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#define SPI_FORCE_CE BIT(4)
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#define SPI_CHIP_SEL_COUNT 7
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#define VENDOR_ID_MCHP 0x1055
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#define SPI_SUSPEND_CONFIG 0x101
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#define SPI_RESUME_CONFIG 0x203
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struct pci1xxxx_spi_internal {
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u8 hw_inst;
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bool spi_xfer_in_progress;
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int irq;
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struct completion spi_xfer_done;
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struct spi_master *spi_host;
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struct pci1xxxx_spi *parent;
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struct {
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unsigned int dev_sel : 3;
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unsigned int msi_vector_sel : 1;
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} prev_val;
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};
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struct pci1xxxx_spi {
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struct pci_dev *dev;
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u8 total_hw_instances;
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void __iomem *reg_base;
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struct pci1xxxx_spi_internal *spi_int[];
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};
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static const struct pci_device_id pci1xxxx_spi_pci_id_table[] = {
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
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{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table);
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static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable)
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{
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struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi->controller);
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struct pci1xxxx_spi *par = p->parent;
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u32 regval;
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/* Set the DEV_SEL bits of the SPI_MST_CTL_REG */
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regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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if (!enable) {
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regval |= SPI_FORCE_CE;
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regval &= ~SPI_MST_CTL_DEVSEL_MASK;
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regval |= (spi->chip_select << 25);
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} else {
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regval &= ~SPI_FORCE_CE;
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}
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writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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}
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static u8 pci1xxxx_get_clock_div(u32 hz)
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{
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u8 val = 0;
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if (hz >= PCI1XXXX_SPI_MAX_CLOCK_HZ)
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val = 2;
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else if ((hz < PCI1XXXX_SPI_MAX_CLOCK_HZ) && (hz >= PCI1XXXX_SPI_CLK_20MHZ))
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val = 3;
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else if ((hz < PCI1XXXX_SPI_CLK_20MHZ) && (hz >= PCI1XXXX_SPI_CLK_15MHZ))
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val = 4;
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else if ((hz < PCI1XXXX_SPI_CLK_15MHZ) && (hz >= PCI1XXXX_SPI_CLK_12MHZ))
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val = 5;
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else if ((hz < PCI1XXXX_SPI_CLK_12MHZ) && (hz >= PCI1XXXX_SPI_CLK_10MHZ))
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val = 6;
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else if ((hz < PCI1XXXX_SPI_CLK_10MHZ) && (hz >= PCI1XXXX_SPI_MIN_CLOCK_HZ))
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val = 7;
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else
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val = 2;
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return val;
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}
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static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
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struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
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int mode, len, loop_iter, transfer_len;
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struct pci1xxxx_spi *par = p->parent;
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unsigned long bytes_transfered;
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unsigned long bytes_recvd;
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unsigned long loop_count;
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u8 *rx_buf, result;
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const u8 *tx_buf;
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u32 regval;
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u8 clkdiv;
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p->spi_xfer_in_progress = true;
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mode = spi->mode;
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clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
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tx_buf = xfer->tx_buf;
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rx_buf = xfer->rx_buf;
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transfer_len = xfer->len;
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regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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if (tx_buf) {
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bytes_transfered = 0;
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bytes_recvd = 0;
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loop_count = transfer_len / SPI_MAX_DATA_LEN;
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if (transfer_len % SPI_MAX_DATA_LEN != 0)
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loop_count += 1;
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for (loop_iter = 0; loop_iter < loop_count; loop_iter++) {
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len = SPI_MAX_DATA_LEN;
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if ((transfer_len % SPI_MAX_DATA_LEN != 0) &&
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(loop_iter == loop_count - 1))
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len = transfer_len % SPI_MAX_DATA_LEN;
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reinit_completion(&p->spi_xfer_done);
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memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst),
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&tx_buf[bytes_transfered], len);
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bytes_transfered += len;
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regval = readl(par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |
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SPI_MST_CTL_SPEED_MASK);
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if (mode == SPI_MODE_3)
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regval |= SPI_MST_CTL_MODE_SEL;
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else
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regval &= ~SPI_MST_CTL_MODE_SEL;
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regval |= (clkdiv << 5);
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regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
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regval |= (len << 8);
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writel(regval, par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval = readl(par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval |= SPI_MST_CTL_GO;
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writel(regval, par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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/* Wait for DMA_TERM interrupt */
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result = wait_for_completion_timeout(&p->spi_xfer_done,
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PCI1XXXX_SPI_TIMEOUT);
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if (!result)
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return -ETIMEDOUT;
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if (rx_buf) {
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memcpy_fromio(&rx_buf[bytes_recvd], par->reg_base +
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SPI_MST_RSP_BUF_OFFSET(p->hw_inst), len);
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bytes_recvd += len;
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}
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}
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}
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p->spi_xfer_in_progress = false;
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return 0;
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}
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static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
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{
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struct pci1xxxx_spi_internal *p = dev;
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irqreturn_t spi_int_fired = IRQ_NONE;
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u32 regval;
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/* Clear the SPI GO_BIT Interrupt */
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regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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if (regval & SPI_INTR) {
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/* Clear xfer_done */
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complete(&p->spi_xfer_done);
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spi_int_fired = IRQ_HANDLED;
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}
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writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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return spi_int_fired;
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}
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static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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u8 hw_inst_cnt, iter, start, only_sec_inst;
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struct pci1xxxx_spi_internal *spi_sub_ptr;
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struct device *dev = &pdev->dev;
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struct pci1xxxx_spi *spi_bus;
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struct spi_master *spi_host;
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u32 regval;
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int ret;
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hw_inst_cnt = ent->driver_data & 0x0f;
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start = (ent->driver_data & 0xf0) >> 4;
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if (start == 1)
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only_sec_inst = 1;
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else
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only_sec_inst = 0;
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spi_bus = devm_kzalloc(&pdev->dev,
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struct_size(spi_bus, spi_int, hw_inst_cnt),
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GFP_KERNEL);
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if (!spi_bus)
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return -ENOMEM;
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spi_bus->dev = pdev;
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spi_bus->total_hw_instances = hw_inst_cnt;
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pci_set_master(pdev);
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for (iter = 0; iter < hw_inst_cnt; iter++) {
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spi_bus->spi_int[iter] = devm_kzalloc(&pdev->dev,
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sizeof(struct pci1xxxx_spi_internal),
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GFP_KERNEL);
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spi_sub_ptr = spi_bus->spi_int[iter];
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spi_sub_ptr->spi_host = devm_spi_alloc_master(dev, sizeof(struct spi_master));
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if (!spi_sub_ptr->spi_host)
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return -ENOMEM;
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spi_sub_ptr->parent = spi_bus;
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spi_sub_ptr->spi_xfer_in_progress = false;
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if (!iter) {
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ret = pcim_enable_device(pdev);
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if (ret)
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return -ENOMEM;
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ret = pci_request_regions(pdev, DRV_NAME);
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if (ret)
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return -ENOMEM;
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spi_bus->reg_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
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if (!spi_bus->reg_base) {
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ret = -EINVAL;
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goto error;
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}
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ret = pci_alloc_irq_vectors(pdev, hw_inst_cnt, hw_inst_cnt,
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PCI_IRQ_ALL_TYPES);
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if (ret < 0) {
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dev_err(&pdev->dev, "Error allocating MSI vectors\n");
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goto error;
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}
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init_completion(&spi_sub_ptr->spi_xfer_done);
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/* Initialize Interrupts - SPI_INT */
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regval = readl(spi_bus->reg_base +
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SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
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regval &= ~SPI_INTR;
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writel(regval, spi_bus->reg_base +
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SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
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spi_sub_ptr->irq = pci_irq_vector(pdev, 0);
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ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
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pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
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pci_name(pdev), spi_sub_ptr);
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if (ret < 0) {
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dev_err(&pdev->dev, "Unable to request irq : %d",
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spi_sub_ptr->irq);
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ret = -ENODEV;
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goto error;
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}
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/* This register is only applicable for 1st instance */
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regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
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if (!only_sec_inst)
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regval |= (BIT(4));
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else
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regval &= ~(BIT(4));
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writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
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}
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spi_sub_ptr->hw_inst = start++;
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if (iter == 1) {
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init_completion(&spi_sub_ptr->spi_xfer_done);
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/* Initialize Interrupts - SPI_INT */
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regval = readl(spi_bus->reg_base +
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SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
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regval &= ~SPI_INTR;
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writel(regval, spi_bus->reg_base +
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SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
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spi_sub_ptr->irq = pci_irq_vector(pdev, iter);
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ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
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pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
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pci_name(pdev), spi_sub_ptr);
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if (ret < 0) {
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dev_err(&pdev->dev, "Unable to request irq : %d",
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spi_sub_ptr->irq);
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ret = -ENODEV;
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goto error;
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}
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}
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spi_host = spi_sub_ptr->spi_host;
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spi_host->num_chipselect = SPI_CHIP_SEL_COUNT;
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spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL |
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SPI_TX_DUAL | SPI_LOOP;
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spi_host->transfer_one = pci1xxxx_spi_transfer_one;
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spi_host->set_cs = pci1xxxx_spi_set_cs;
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spi_host->bits_per_word_mask = SPI_BPW_MASK(8);
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spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;
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spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ;
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spi_host->flags = SPI_MASTER_MUST_TX;
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spi_master_set_devdata(spi_host, spi_sub_ptr);
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ret = devm_spi_register_master(dev, spi_host);
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if (ret)
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goto error;
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}
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pci_set_drvdata(pdev, spi_bus);
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return 0;
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error:
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pci_release_regions(pdev);
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return ret;
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}
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static void store_restore_config(struct pci1xxxx_spi *spi_ptr,
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struct pci1xxxx_spi_internal *spi_sub_ptr,
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u8 inst, bool store)
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{
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u32 regval;
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if (store) {
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regval = readl(spi_ptr->reg_base +
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SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst));
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regval &= SPI_MST_CTL_DEVSEL_MASK;
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spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7;
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regval = readl(spi_ptr->reg_base +
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SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst));
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regval &= SPI_MSI_VECTOR_SEL_MASK;
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spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1;
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} else {
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regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
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regval &= ~SPI_MST_CTL_DEVSEL_MASK;
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regval |= (spi_sub_ptr->prev_val.dev_sel << 25);
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writel(regval,
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spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
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writel((spi_sub_ptr->prev_val.msi_vector_sel << 4),
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spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst));
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|
}
|
|
}
|
|
|
|
static int pci1xxxx_spi_resume(struct device *dev)
|
|
{
|
|
struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
|
|
struct pci1xxxx_spi_internal *spi_sub_ptr;
|
|
u32 regval = SPI_RESUME_CONFIG;
|
|
u8 iter;
|
|
|
|
for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
|
|
spi_sub_ptr = spi_ptr->spi_int[iter];
|
|
spi_master_resume(spi_sub_ptr->spi_host);
|
|
writel(regval, spi_ptr->reg_base +
|
|
SPI_MST_EVENT_MASK_REG_OFFSET(iter));
|
|
|
|
/* Restore config at resume */
|
|
store_restore_config(spi_ptr, spi_sub_ptr, iter, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci1xxxx_spi_suspend(struct device *dev)
|
|
{
|
|
struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
|
|
struct pci1xxxx_spi_internal *spi_sub_ptr;
|
|
u32 reg1 = SPI_SUSPEND_CONFIG;
|
|
u8 iter;
|
|
|
|
for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
|
|
spi_sub_ptr = spi_ptr->spi_int[iter];
|
|
|
|
while (spi_sub_ptr->spi_xfer_in_progress)
|
|
msleep(20);
|
|
|
|
/* Store existing config before suspend */
|
|
store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);
|
|
spi_master_suspend(spi_sub_ptr->spi_host);
|
|
writel(reg1, spi_ptr->reg_base +
|
|
SPI_MST_EVENT_MASK_REG_OFFSET(iter));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend,
|
|
pci1xxxx_spi_resume);
|
|
|
|
static struct pci_driver pci1xxxx_spi_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = pci1xxxx_spi_pci_id_table,
|
|
.probe = pci1xxxx_spi_probe,
|
|
.driver = {
|
|
.pm = pm_sleep_ptr(&spi_pm_ops),
|
|
},
|
|
};
|
|
|
|
module_pci_driver(pci1xxxx_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx SPI bus driver");
|
|
MODULE_AUTHOR("Tharun Kumar P<tharunkumar.pasumarthi@microchip.com>");
|
|
MODULE_AUTHOR("Kumaravel Thiagarajan<kumaravel.thiagarajan@microchip.com>");
|
|
MODULE_LICENSE("GPL v2");
|