628 lines
16 KiB
C
628 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* dwc3-omap.c - OMAP Specific Glue layer
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/dma-mapping.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/extcon.h>
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#include <linux/regulator/consumer.h>
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#include <linux/usb/otg.h>
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/*
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* All these registers belong to OMAP's Wrapper around the
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* DesignWare USB3 Core.
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*/
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#define USBOTGSS_REVISION 0x0000
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#define USBOTGSS_SYSCONFIG 0x0010
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#define USBOTGSS_IRQ_EOI 0x0020
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#define USBOTGSS_EOI_OFFSET 0x0008
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#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
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#define USBOTGSS_IRQSTATUS_0 0x0028
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#define USBOTGSS_IRQENABLE_SET_0 0x002c
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#define USBOTGSS_IRQENABLE_CLR_0 0x0030
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#define USBOTGSS_IRQ0_OFFSET 0x0004
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#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
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#define USBOTGSS_IRQSTATUS_1 0x0034
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#define USBOTGSS_IRQENABLE_SET_1 0x0038
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#define USBOTGSS_IRQENABLE_CLR_1 0x003c
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#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
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#define USBOTGSS_IRQSTATUS_2 0x0044
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#define USBOTGSS_IRQENABLE_SET_2 0x0048
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#define USBOTGSS_IRQENABLE_CLR_2 0x004c
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#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
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#define USBOTGSS_IRQSTATUS_3 0x0054
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#define USBOTGSS_IRQENABLE_SET_3 0x0058
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#define USBOTGSS_IRQENABLE_CLR_3 0x005c
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#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
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#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
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#define USBOTGSS_IRQSTATUS_MISC 0x0038
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#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
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#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
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#define USBOTGSS_IRQMISC_OFFSET 0x03fc
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#define USBOTGSS_UTMI_OTG_STATUS 0x0080
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#define USBOTGSS_UTMI_OTG_CTRL 0x0084
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#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
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#define USBOTGSS_TXFIFO_DEPTH 0x0508
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#define USBOTGSS_RXFIFO_DEPTH 0x050c
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#define USBOTGSS_MMRAM_OFFSET 0x0100
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#define USBOTGSS_FLADJ 0x0104
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#define USBOTGSS_DEBUG_CFG 0x0108
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#define USBOTGSS_DEBUG_DATA 0x010c
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#define USBOTGSS_DEV_EBC_EN 0x0110
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#define USBOTGSS_DEBUG_OFFSET 0x0600
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/* SYSCONFIG REGISTER */
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#define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16)
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/* IRQ_EOI REGISTER */
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#define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0)
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/* IRQS0 BITS */
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#define USBOTGSS_IRQO_COREIRQ_ST BIT(0)
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/* IRQMISC BITS */
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#define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17)
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#define USBOTGSS_IRQMISC_OEVT BIT(16)
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#define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13)
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#define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12)
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#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11)
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#define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8)
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#define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5)
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#define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4)
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#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3)
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#define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0)
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/* UTMI_OTG_STATUS REGISTER */
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#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5)
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#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4)
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#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3)
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#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0)
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/* UTMI_OTG_CTRL REGISTER */
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#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31)
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#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9)
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#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8)
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#define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4)
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#define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3)
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#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2)
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#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1)
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enum dwc3_omap_utmi_mode {
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DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
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DWC3_OMAP_UTMI_MODE_HW,
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DWC3_OMAP_UTMI_MODE_SW,
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};
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struct dwc3_omap {
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struct device *dev;
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int irq;
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void __iomem *base;
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u32 utmi_otg_ctrl;
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u32 utmi_otg_offset;
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u32 irqmisc_offset;
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u32 irq_eoi_offset;
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u32 debug_offset;
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u32 irq0_offset;
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struct extcon_dev *edev;
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struct notifier_block vbus_nb;
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struct notifier_block id_nb;
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struct regulator *vbus_reg;
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};
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enum omap_dwc3_vbus_id_status {
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OMAP_DWC3_ID_FLOAT,
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OMAP_DWC3_ID_GROUND,
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OMAP_DWC3_VBUS_OFF,
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OMAP_DWC3_VBUS_VALID,
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};
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static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
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{
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writel(value, base + offset);
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}
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static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
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omap->utmi_otg_offset);
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}
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static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
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omap->utmi_otg_offset, value);
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}
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static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
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omap->irq0_offset);
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}
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static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
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omap->irq0_offset, value);
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}
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static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
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omap->irqmisc_offset);
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}
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static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
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omap->irq0_offset, value);
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}
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static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
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omap->irq0_offset, value);
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}
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static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
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enum omap_dwc3_vbus_id_status status)
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{
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int ret;
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u32 val;
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switch (status) {
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case OMAP_DWC3_ID_GROUND:
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if (omap->vbus_reg) {
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ret = regulator_enable(omap->vbus_reg);
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if (ret) {
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dev_err(omap->dev, "regulator enable failed\n");
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return;
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}
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}
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val = dwc3_omap_read_utmi_ctrl(omap);
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val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
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dwc3_omap_write_utmi_ctrl(omap, val);
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break;
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case OMAP_DWC3_VBUS_VALID:
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val = dwc3_omap_read_utmi_ctrl(omap);
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val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
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val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
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| USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
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dwc3_omap_write_utmi_ctrl(omap, val);
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break;
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case OMAP_DWC3_ID_FLOAT:
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if (omap->vbus_reg && regulator_is_enabled(omap->vbus_reg))
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regulator_disable(omap->vbus_reg);
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val = dwc3_omap_read_utmi_ctrl(omap);
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val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
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dwc3_omap_write_utmi_ctrl(omap, val);
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break;
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case OMAP_DWC3_VBUS_OFF:
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val = dwc3_omap_read_utmi_ctrl(omap);
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val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
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| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
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val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
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dwc3_omap_write_utmi_ctrl(omap, val);
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break;
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default:
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dev_WARN(omap->dev, "invalid state\n");
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}
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}
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static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
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static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
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static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
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{
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struct dwc3_omap *omap = _omap;
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if (dwc3_omap_read_irqmisc_status(omap) ||
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dwc3_omap_read_irq0_status(omap)) {
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/* mask irqs */
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dwc3_omap_disable_irqs(omap);
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return IRQ_WAKE_THREAD;
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}
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return IRQ_NONE;
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}
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static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
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{
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struct dwc3_omap *omap = _omap;
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u32 reg;
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/* clear irq status flags */
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reg = dwc3_omap_read_irqmisc_status(omap);
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dwc3_omap_write_irqmisc_status(omap, reg);
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reg = dwc3_omap_read_irq0_status(omap);
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dwc3_omap_write_irq0_status(omap, reg);
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/* unmask irqs */
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dwc3_omap_enable_irqs(omap);
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return IRQ_HANDLED;
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}
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static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
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{
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u32 reg;
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/* enable all IRQs */
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reg = USBOTGSS_IRQO_COREIRQ_ST;
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dwc3_omap_write_irq0_set(omap, reg);
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reg = (USBOTGSS_IRQMISC_OEVT |
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USBOTGSS_IRQMISC_DRVVBUS_RISE |
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USBOTGSS_IRQMISC_CHRGVBUS_RISE |
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USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
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USBOTGSS_IRQMISC_IDPULLUP_RISE |
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USBOTGSS_IRQMISC_DRVVBUS_FALL |
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USBOTGSS_IRQMISC_CHRGVBUS_FALL |
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USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
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USBOTGSS_IRQMISC_IDPULLUP_FALL);
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dwc3_omap_write_irqmisc_set(omap, reg);
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}
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static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
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{
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u32 reg;
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/* disable all IRQs */
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reg = USBOTGSS_IRQO_COREIRQ_ST;
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dwc3_omap_write_irq0_clr(omap, reg);
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reg = (USBOTGSS_IRQMISC_OEVT |
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USBOTGSS_IRQMISC_DRVVBUS_RISE |
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USBOTGSS_IRQMISC_CHRGVBUS_RISE |
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USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
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USBOTGSS_IRQMISC_IDPULLUP_RISE |
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USBOTGSS_IRQMISC_DRVVBUS_FALL |
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USBOTGSS_IRQMISC_CHRGVBUS_FALL |
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USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
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USBOTGSS_IRQMISC_IDPULLUP_FALL);
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dwc3_omap_write_irqmisc_clr(omap, reg);
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}
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static int dwc3_omap_id_notifier(struct notifier_block *nb,
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unsigned long event, void *ptr)
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{
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struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
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if (event)
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dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
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else
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dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
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return NOTIFY_DONE;
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}
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static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
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unsigned long event, void *ptr)
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{
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struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
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if (event)
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dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
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else
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dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
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return NOTIFY_DONE;
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}
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static void dwc3_omap_map_offset(struct dwc3_omap *omap)
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{
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struct device_node *node = omap->dev->of_node;
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/*
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* Differentiate between OMAP5 and AM437x.
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*
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* For OMAP5(ES2.0) and AM437x wrapper revision is same, even
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* though there are changes in wrapper register offsets.
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*
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* Using dt compatible to differentiate AM437x.
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*/
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if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
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omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
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omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
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omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
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omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
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omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
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}
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}
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static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
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{
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u32 reg;
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struct device_node *node = omap->dev->of_node;
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u32 utmi_mode = 0;
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reg = dwc3_omap_read_utmi_ctrl(omap);
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of_property_read_u32(node, "utmi-mode", &utmi_mode);
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switch (utmi_mode) {
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case DWC3_OMAP_UTMI_MODE_SW:
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reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
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break;
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case DWC3_OMAP_UTMI_MODE_HW:
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reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
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break;
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default:
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dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
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}
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dwc3_omap_write_utmi_ctrl(omap, reg);
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}
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static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
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{
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int ret;
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struct device_node *node = omap->dev->of_node;
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struct extcon_dev *edev;
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if (of_property_read_bool(node, "extcon")) {
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edev = extcon_get_edev_by_phandle(omap->dev, 0);
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if (IS_ERR(edev)) {
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dev_vdbg(omap->dev, "couldn't get extcon device\n");
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return -EPROBE_DEFER;
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}
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omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
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ret = devm_extcon_register_notifier(omap->dev, edev,
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EXTCON_USB, &omap->vbus_nb);
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if (ret < 0)
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dev_vdbg(omap->dev, "failed to register notifier for USB\n");
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omap->id_nb.notifier_call = dwc3_omap_id_notifier;
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ret = devm_extcon_register_notifier(omap->dev, edev,
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EXTCON_USB_HOST, &omap->id_nb);
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if (ret < 0)
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dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
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if (extcon_get_state(edev, EXTCON_USB) == true)
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
|
|
else
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
|
|
|
|
if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
|
|
else
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
|
|
|
|
omap->edev = edev;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_omap_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
|
struct dwc3_omap *omap;
|
|
struct device *dev = &pdev->dev;
|
|
struct regulator *vbus_reg = NULL;
|
|
|
|
int ret;
|
|
int irq;
|
|
|
|
void __iomem *base;
|
|
|
|
if (!node) {
|
|
dev_err(dev, "device node not found\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
|
|
if (!omap)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, omap);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
if (of_property_read_bool(node, "vbus-supply")) {
|
|
vbus_reg = devm_regulator_get(dev, "vbus");
|
|
if (IS_ERR(vbus_reg)) {
|
|
dev_err(dev, "vbus init failed\n");
|
|
return PTR_ERR(vbus_reg);
|
|
}
|
|
}
|
|
|
|
omap->dev = dev;
|
|
omap->irq = irq;
|
|
omap->base = base;
|
|
omap->vbus_reg = vbus_reg;
|
|
|
|
pm_runtime_enable(dev);
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "get_sync failed with err %d\n", ret);
|
|
goto err1;
|
|
}
|
|
|
|
dwc3_omap_map_offset(omap);
|
|
dwc3_omap_set_utmi_mode(omap);
|
|
|
|
ret = dwc3_omap_extcon_register(omap);
|
|
if (ret < 0)
|
|
goto err1;
|
|
|
|
ret = of_platform_populate(node, NULL, NULL, dev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to create dwc3 core\n");
|
|
goto err1;
|
|
}
|
|
|
|
ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
|
|
dwc3_omap_interrupt_thread, IRQF_SHARED,
|
|
"dwc3-omap", omap);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request IRQ #%d --> %d\n",
|
|
omap->irq, ret);
|
|
goto err1;
|
|
}
|
|
dwc3_omap_enable_irqs(omap);
|
|
return 0;
|
|
|
|
err1:
|
|
pm_runtime_put_sync(dev);
|
|
pm_runtime_disable(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_omap_remove(struct platform_device *pdev)
|
|
{
|
|
struct dwc3_omap *omap = platform_get_drvdata(pdev);
|
|
|
|
dwc3_omap_disable_irqs(omap);
|
|
disable_irq(omap->irq);
|
|
of_platform_depopulate(omap->dev);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id of_dwc3_match[] = {
|
|
{
|
|
.compatible = "ti,dwc3"
|
|
},
|
|
{
|
|
.compatible = "ti,am437x-dwc3"
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_dwc3_match);
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dwc3_omap_suspend(struct device *dev)
|
|
{
|
|
struct dwc3_omap *omap = dev_get_drvdata(dev);
|
|
|
|
omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
|
|
dwc3_omap_disable_irqs(omap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_omap_resume(struct device *dev)
|
|
{
|
|
struct dwc3_omap *omap = dev_get_drvdata(dev);
|
|
|
|
dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
|
|
dwc3_omap_enable_irqs(omap);
|
|
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_omap_complete(struct device *dev)
|
|
{
|
|
struct dwc3_omap *omap = dev_get_drvdata(dev);
|
|
|
|
if (extcon_get_state(omap->edev, EXTCON_USB))
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
|
|
else
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
|
|
|
|
if (extcon_get_state(omap->edev, EXTCON_USB_HOST))
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
|
|
else
|
|
dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
|
|
}
|
|
|
|
static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
|
|
.complete = dwc3_omap_complete,
|
|
};
|
|
|
|
#define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
|
|
#else
|
|
#define DEV_PM_OPS NULL
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static struct platform_driver dwc3_omap_driver = {
|
|
.probe = dwc3_omap_probe,
|
|
.remove = dwc3_omap_remove,
|
|
.driver = {
|
|
.name = "omap-dwc3",
|
|
.of_match_table = of_dwc3_match,
|
|
.pm = DEV_PM_OPS,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(dwc3_omap_driver);
|
|
|
|
MODULE_ALIAS("platform:omap-dwc3");
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
|