4094 lines
99 KiB
C
4094 lines
99 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/drivers/video/omap2/dss/dispc.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*/
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#define DSS_SUBSYS_NAME "DISPC"
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#include <linux/kernel.h>
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#include <linux/dma-mapping.h>
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#include <linux/vmalloc.h>
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/seq_file.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/hardirq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sizes.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/of.h>
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#include <linux/component.h>
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#include <video/omapfb_dss.h>
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#include "dss.h"
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#include "dss_features.h"
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#include "dispc.h"
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/* DISPC */
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#define DISPC_SZ_REGS SZ_4K
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enum omap_burst_size {
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BURST_SIZE_X2 = 0,
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BURST_SIZE_X4 = 1,
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BURST_SIZE_X8 = 2,
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};
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#define REG_GET(idx, start, end) \
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FLD_GET(dispc_read_reg(idx), start, end)
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#define REG_FLD_MOD(idx, val, start, end) \
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dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
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struct dispc_features {
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u8 sw_start;
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u8 fp_start;
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u8 bp_start;
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u16 sw_max;
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u16 vp_max;
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u16 hp_max;
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u8 mgr_width_start;
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u8 mgr_height_start;
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u16 mgr_width_max;
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u16 mgr_height_max;
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unsigned long max_lcd_pclk;
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unsigned long max_tv_pclk;
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int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
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const struct omap_video_timings *mgr_timings,
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u16 width, u16 height, u16 out_width, u16 out_height,
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enum omap_color_mode color_mode, bool *five_taps,
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int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
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u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
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unsigned long (*calc_core_clk) (unsigned long pclk,
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u16 width, u16 height, u16 out_width, u16 out_height,
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bool mem_to_mem);
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u8 num_fifos;
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/* swap GFX & WB fifos */
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bool gfx_fifo_workaround:1;
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/* no DISPC_IRQ_FRAMEDONETV on this SoC */
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bool no_framedone_tv:1;
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/* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
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bool mstandby_workaround:1;
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bool set_max_preload:1;
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/* PIXEL_INC is not added to the last pixel of a line */
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bool last_pixel_inc_missing:1;
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/* POL_FREQ has ALIGN bit */
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bool supports_sync_align:1;
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bool has_writeback:1;
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};
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#define DISPC_MAX_NR_FIFOS 5
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static struct {
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struct platform_device *pdev;
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void __iomem *base;
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int irq;
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irq_handler_t user_handler;
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void *user_data;
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unsigned long core_clk_rate;
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unsigned long tv_pclk_rate;
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u32 fifo_size[DISPC_MAX_NR_FIFOS];
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/* maps which plane is using a fifo. fifo-id -> plane-id */
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int fifo_assignment[DISPC_MAX_NR_FIFOS];
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bool ctx_valid;
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u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
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const struct dispc_features *feat;
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bool is_enabled;
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struct regmap *syscon_pol;
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u32 syscon_pol_offset;
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/* DISPC_CONTROL & DISPC_CONFIG lock*/
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spinlock_t control_lock;
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} dispc;
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enum omap_color_component {
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/* used for all color formats for OMAP3 and earlier
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* and for RGB and Y color component on OMAP4
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*/
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DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
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/* used for UV component for
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* OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
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* color formats on OMAP4
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*/
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DISPC_COLOR_COMPONENT_UV = 1 << 1,
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};
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enum mgr_reg_fields {
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DISPC_MGR_FLD_ENABLE,
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DISPC_MGR_FLD_STNTFT,
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DISPC_MGR_FLD_GO,
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DISPC_MGR_FLD_TFTDATALINES,
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DISPC_MGR_FLD_STALLMODE,
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DISPC_MGR_FLD_TCKENABLE,
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DISPC_MGR_FLD_TCKSELECTION,
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DISPC_MGR_FLD_CPR,
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DISPC_MGR_FLD_FIFOHANDCHECK,
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/* used to maintain a count of the above fields */
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DISPC_MGR_FLD_NUM,
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};
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struct dispc_reg_field {
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u16 reg;
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u8 high;
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u8 low;
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};
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static const struct {
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const char *name;
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u32 vsync_irq;
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u32 framedone_irq;
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u32 sync_lost_irq;
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struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
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} mgr_desc[] = {
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[OMAP_DSS_CHANNEL_LCD] = {
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.name = "LCD",
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.vsync_irq = DISPC_IRQ_VSYNC,
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.framedone_irq = DISPC_IRQ_FRAMEDONE,
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.sync_lost_irq = DISPC_IRQ_SYNC_LOST,
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.reg_desc = {
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[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
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[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
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[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
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[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
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[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
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[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
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[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
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[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
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[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
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},
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},
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[OMAP_DSS_CHANNEL_DIGIT] = {
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.name = "DIGIT",
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.vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
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.framedone_irq = DISPC_IRQ_FRAMEDONETV,
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.sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
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.reg_desc = {
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[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
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[DISPC_MGR_FLD_STNTFT] = { },
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[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
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[DISPC_MGR_FLD_TFTDATALINES] = { },
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[DISPC_MGR_FLD_STALLMODE] = { },
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[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
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[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
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[DISPC_MGR_FLD_CPR] = { },
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[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
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},
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},
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[OMAP_DSS_CHANNEL_LCD2] = {
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.name = "LCD2",
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.vsync_irq = DISPC_IRQ_VSYNC2,
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.framedone_irq = DISPC_IRQ_FRAMEDONE2,
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.sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
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.reg_desc = {
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[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
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[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
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[DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
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[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
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[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
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[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
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[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
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[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
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[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
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},
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},
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[OMAP_DSS_CHANNEL_LCD3] = {
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.name = "LCD3",
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.vsync_irq = DISPC_IRQ_VSYNC3,
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.framedone_irq = DISPC_IRQ_FRAMEDONE3,
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.sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
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.reg_desc = {
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[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
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[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
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[DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
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[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
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[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
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[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
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[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
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[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
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[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
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},
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},
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};
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struct color_conv_coef {
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int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
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int full_range;
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};
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static unsigned long dispc_fclk_rate(void);
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static unsigned long dispc_core_clk_rate(void);
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static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
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static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
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static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
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static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
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static inline void dispc_write_reg(const u16 idx, u32 val)
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{
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__raw_writel(val, dispc.base + idx);
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}
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static inline u32 dispc_read_reg(const u16 idx)
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{
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return __raw_readl(dispc.base + idx);
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}
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static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
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{
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const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
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return REG_GET(rfld.reg, rfld.high, rfld.low);
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}
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static void mgr_fld_write(enum omap_channel channel,
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enum mgr_reg_fields regfld, int val) {
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const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
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const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
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unsigned long flags;
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if (need_lock)
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spin_lock_irqsave(&dispc.control_lock, flags);
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REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
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if (need_lock)
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spin_unlock_irqrestore(&dispc.control_lock, flags);
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}
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#define SR(reg) \
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dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
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#define RR(reg) \
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dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
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static void dispc_save_context(void)
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{
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int i, j;
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DSSDBG("dispc_save_context\n");
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SR(IRQENABLE);
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SR(CONTROL);
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SR(CONFIG);
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SR(LINE_NUMBER);
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if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
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dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
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SR(GLOBAL_ALPHA);
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if (dss_has_feature(FEAT_MGR_LCD2)) {
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SR(CONTROL2);
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SR(CONFIG2);
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}
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if (dss_has_feature(FEAT_MGR_LCD3)) {
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SR(CONTROL3);
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SR(CONFIG3);
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}
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for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
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SR(DEFAULT_COLOR(i));
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SR(TRANS_COLOR(i));
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SR(SIZE_MGR(i));
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if (i == OMAP_DSS_CHANNEL_DIGIT)
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continue;
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SR(TIMING_H(i));
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SR(TIMING_V(i));
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SR(POL_FREQ(i));
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SR(DIVISORo(i));
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SR(DATA_CYCLE1(i));
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SR(DATA_CYCLE2(i));
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SR(DATA_CYCLE3(i));
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if (dss_has_feature(FEAT_CPR)) {
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SR(CPR_COEF_R(i));
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SR(CPR_COEF_G(i));
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SR(CPR_COEF_B(i));
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}
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}
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for (i = 0; i < dss_feat_get_num_ovls(); i++) {
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SR(OVL_BA0(i));
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SR(OVL_BA1(i));
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SR(OVL_POSITION(i));
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SR(OVL_SIZE(i));
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SR(OVL_ATTRIBUTES(i));
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SR(OVL_FIFO_THRESHOLD(i));
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SR(OVL_ROW_INC(i));
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SR(OVL_PIXEL_INC(i));
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if (dss_has_feature(FEAT_PRELOAD))
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SR(OVL_PRELOAD(i));
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if (i == OMAP_DSS_GFX) {
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SR(OVL_WINDOW_SKIP(i));
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SR(OVL_TABLE_BA(i));
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continue;
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}
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SR(OVL_FIR(i));
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SR(OVL_PICTURE_SIZE(i));
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SR(OVL_ACCU0(i));
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SR(OVL_ACCU1(i));
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for (j = 0; j < 8; j++)
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SR(OVL_FIR_COEF_H(i, j));
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for (j = 0; j < 8; j++)
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SR(OVL_FIR_COEF_HV(i, j));
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for (j = 0; j < 5; j++)
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SR(OVL_CONV_COEF(i, j));
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if (dss_has_feature(FEAT_FIR_COEF_V)) {
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for (j = 0; j < 8; j++)
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SR(OVL_FIR_COEF_V(i, j));
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}
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if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
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SR(OVL_BA0_UV(i));
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SR(OVL_BA1_UV(i));
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SR(OVL_FIR2(i));
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SR(OVL_ACCU2_0(i));
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SR(OVL_ACCU2_1(i));
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for (j = 0; j < 8; j++)
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SR(OVL_FIR_COEF_H2(i, j));
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for (j = 0; j < 8; j++)
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SR(OVL_FIR_COEF_HV2(i, j));
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for (j = 0; j < 8; j++)
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SR(OVL_FIR_COEF_V2(i, j));
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}
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if (dss_has_feature(FEAT_ATTR2))
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SR(OVL_ATTRIBUTES2(i));
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}
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if (dss_has_feature(FEAT_CORE_CLK_DIV))
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SR(DIVISOR);
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dispc.ctx_valid = true;
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DSSDBG("context saved\n");
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}
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static void dispc_restore_context(void)
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{
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int i, j;
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DSSDBG("dispc_restore_context\n");
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if (!dispc.ctx_valid)
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return;
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/*RR(IRQENABLE);*/
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/*RR(CONTROL);*/
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RR(CONFIG);
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RR(LINE_NUMBER);
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if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
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dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
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RR(GLOBAL_ALPHA);
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if (dss_has_feature(FEAT_MGR_LCD2))
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RR(CONFIG2);
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if (dss_has_feature(FEAT_MGR_LCD3))
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RR(CONFIG3);
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for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
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RR(DEFAULT_COLOR(i));
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RR(TRANS_COLOR(i));
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RR(SIZE_MGR(i));
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if (i == OMAP_DSS_CHANNEL_DIGIT)
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continue;
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RR(TIMING_H(i));
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RR(TIMING_V(i));
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RR(POL_FREQ(i));
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RR(DIVISORo(i));
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RR(DATA_CYCLE1(i));
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RR(DATA_CYCLE2(i));
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RR(DATA_CYCLE3(i));
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if (dss_has_feature(FEAT_CPR)) {
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RR(CPR_COEF_R(i));
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RR(CPR_COEF_G(i));
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RR(CPR_COEF_B(i));
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}
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}
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for (i = 0; i < dss_feat_get_num_ovls(); i++) {
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RR(OVL_BA0(i));
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RR(OVL_BA1(i));
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RR(OVL_POSITION(i));
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RR(OVL_SIZE(i));
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RR(OVL_ATTRIBUTES(i));
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RR(OVL_FIFO_THRESHOLD(i));
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RR(OVL_ROW_INC(i));
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RR(OVL_PIXEL_INC(i));
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if (dss_has_feature(FEAT_PRELOAD))
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RR(OVL_PRELOAD(i));
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if (i == OMAP_DSS_GFX) {
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RR(OVL_WINDOW_SKIP(i));
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RR(OVL_TABLE_BA(i));
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continue;
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}
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RR(OVL_FIR(i));
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RR(OVL_PICTURE_SIZE(i));
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RR(OVL_ACCU0(i));
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|
RR(OVL_ACCU1(i));
|
|
|
|
for (j = 0; j < 8; j++)
|
|
RR(OVL_FIR_COEF_H(i, j));
|
|
|
|
for (j = 0; j < 8; j++)
|
|
RR(OVL_FIR_COEF_HV(i, j));
|
|
|
|
for (j = 0; j < 5; j++)
|
|
RR(OVL_CONV_COEF(i, j));
|
|
|
|
if (dss_has_feature(FEAT_FIR_COEF_V)) {
|
|
for (j = 0; j < 8; j++)
|
|
RR(OVL_FIR_COEF_V(i, j));
|
|
}
|
|
|
|
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
|
|
RR(OVL_BA0_UV(i));
|
|
RR(OVL_BA1_UV(i));
|
|
RR(OVL_FIR2(i));
|
|
RR(OVL_ACCU2_0(i));
|
|
RR(OVL_ACCU2_1(i));
|
|
|
|
for (j = 0; j < 8; j++)
|
|
RR(OVL_FIR_COEF_H2(i, j));
|
|
|
|
for (j = 0; j < 8; j++)
|
|
RR(OVL_FIR_COEF_HV2(i, j));
|
|
|
|
for (j = 0; j < 8; j++)
|
|
RR(OVL_FIR_COEF_V2(i, j));
|
|
}
|
|
if (dss_has_feature(FEAT_ATTR2))
|
|
RR(OVL_ATTRIBUTES2(i));
|
|
}
|
|
|
|
if (dss_has_feature(FEAT_CORE_CLK_DIV))
|
|
RR(DIVISOR);
|
|
|
|
/* enable last, because LCD & DIGIT enable are here */
|
|
RR(CONTROL);
|
|
if (dss_has_feature(FEAT_MGR_LCD2))
|
|
RR(CONTROL2);
|
|
if (dss_has_feature(FEAT_MGR_LCD3))
|
|
RR(CONTROL3);
|
|
/* clear spurious SYNC_LOST_DIGIT interrupts */
|
|
dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
|
|
|
|
/*
|
|
* enable last so IRQs won't trigger before
|
|
* the context is fully restored
|
|
*/
|
|
RR(IRQENABLE);
|
|
|
|
DSSDBG("context restored\n");
|
|
}
|
|
|
|
#undef SR
|
|
#undef RR
|
|
|
|
int dispc_runtime_get(void)
|
|
{
|
|
int r;
|
|
|
|
DSSDBG("dispc_runtime_get\n");
|
|
|
|
r = pm_runtime_resume_and_get(&dispc.pdev->dev);
|
|
if (WARN_ON(r < 0))
|
|
return r;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(dispc_runtime_get);
|
|
|
|
void dispc_runtime_put(void)
|
|
{
|
|
int r;
|
|
|
|
DSSDBG("dispc_runtime_put\n");
|
|
|
|
r = pm_runtime_put_sync(&dispc.pdev->dev);
|
|
WARN_ON(r < 0 && r != -ENOSYS);
|
|
}
|
|
EXPORT_SYMBOL(dispc_runtime_put);
|
|
|
|
u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
|
|
{
|
|
return mgr_desc[channel].vsync_irq;
|
|
}
|
|
EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
|
|
|
|
u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
|
|
{
|
|
if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
|
|
return 0;
|
|
|
|
return mgr_desc[channel].framedone_irq;
|
|
}
|
|
EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
|
|
|
|
u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
|
|
{
|
|
return mgr_desc[channel].sync_lost_irq;
|
|
}
|
|
EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
|
|
|
|
bool dispc_mgr_go_busy(enum omap_channel channel)
|
|
{
|
|
return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
|
|
}
|
|
EXPORT_SYMBOL(dispc_mgr_go_busy);
|
|
|
|
void dispc_mgr_go(enum omap_channel channel)
|
|
{
|
|
WARN_ON(!dispc_mgr_is_enabled(channel));
|
|
WARN_ON(dispc_mgr_go_busy(channel));
|
|
|
|
DSSDBG("GO %s\n", mgr_desc[channel].name);
|
|
|
|
mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
|
|
}
|
|
EXPORT_SYMBOL(dispc_mgr_go);
|
|
|
|
static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
|
|
}
|
|
|
|
static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
|
|
}
|
|
|
|
static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
|
|
}
|
|
|
|
static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
|
|
{
|
|
BUG_ON(plane == OMAP_DSS_GFX);
|
|
|
|
dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
|
|
}
|
|
|
|
static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
|
|
u32 value)
|
|
{
|
|
BUG_ON(plane == OMAP_DSS_GFX);
|
|
|
|
dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
|
|
}
|
|
|
|
static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
|
|
{
|
|
BUG_ON(plane == OMAP_DSS_GFX);
|
|
|
|
dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
|
|
}
|
|
|
|
static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
|
|
int fir_vinc, int five_taps,
|
|
enum omap_color_component color_comp)
|
|
{
|
|
const struct dispc_coef *h_coef, *v_coef;
|
|
int i;
|
|
|
|
h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
|
|
v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
u32 h, hv;
|
|
|
|
h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
|
|
| FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
|
|
| FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
|
|
| FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
|
|
hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
|
|
| FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
|
|
| FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
|
|
| FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
|
|
|
|
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
|
|
dispc_ovl_write_firh_reg(plane, i, h);
|
|
dispc_ovl_write_firhv_reg(plane, i, hv);
|
|
} else {
|
|
dispc_ovl_write_firh2_reg(plane, i, h);
|
|
dispc_ovl_write_firhv2_reg(plane, i, hv);
|
|
}
|
|
|
|
}
|
|
|
|
if (five_taps) {
|
|
for (i = 0; i < 8; i++) {
|
|
u32 v;
|
|
v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
|
|
| FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
|
|
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
|
|
dispc_ovl_write_firv_reg(plane, i, v);
|
|
else
|
|
dispc_ovl_write_firv2_reg(plane, i, v);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
|
|
const struct color_conv_coef *ct)
|
|
{
|
|
#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
|
|
|
|
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
|
|
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
|
|
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
|
|
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
|
|
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
|
|
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
|
|
|
|
#undef CVAL
|
|
}
|
|
|
|
static void dispc_setup_color_conv_coef(void)
|
|
{
|
|
int i;
|
|
int num_ovl = dss_feat_get_num_ovls();
|
|
const struct color_conv_coef ctbl_bt601_5_ovl = {
|
|
/* YUV -> RGB */
|
|
298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
|
|
};
|
|
const struct color_conv_coef ctbl_bt601_5_wb = {
|
|
/* RGB -> YUV */
|
|
66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
|
|
};
|
|
|
|
for (i = 1; i < num_ovl; i++)
|
|
dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
|
|
|
|
if (dispc.feat->has_writeback)
|
|
dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
|
|
}
|
|
|
|
static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
|
|
}
|
|
|
|
static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
|
|
}
|
|
|
|
static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
|
|
}
|
|
|
|
static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
|
|
}
|
|
|
|
static void dispc_ovl_set_pos(enum omap_plane plane,
|
|
enum omap_overlay_caps caps, int x, int y)
|
|
{
|
|
u32 val;
|
|
|
|
if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
|
|
return;
|
|
|
|
val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
|
|
|
|
dispc_write_reg(DISPC_OVL_POSITION(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
|
|
int height)
|
|
{
|
|
u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
|
|
|
|
if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
|
|
dispc_write_reg(DISPC_OVL_SIZE(plane), val);
|
|
else
|
|
dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
|
|
int height)
|
|
{
|
|
u32 val;
|
|
|
|
BUG_ON(plane == OMAP_DSS_GFX);
|
|
|
|
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
|
|
|
|
if (plane == OMAP_DSS_WB)
|
|
dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
|
|
else
|
|
dispc_write_reg(DISPC_OVL_SIZE(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_set_zorder(enum omap_plane plane,
|
|
enum omap_overlay_caps caps, u8 zorder)
|
|
{
|
|
if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
|
|
return;
|
|
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
|
|
}
|
|
|
|
static void dispc_ovl_enable_zorder_planes(void)
|
|
{
|
|
int i;
|
|
|
|
if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
|
|
return;
|
|
|
|
for (i = 0; i < dss_feat_get_num_ovls(); i++)
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
|
|
}
|
|
|
|
static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
|
|
enum omap_overlay_caps caps, bool enable)
|
|
{
|
|
if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
|
|
return;
|
|
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
|
|
}
|
|
|
|
static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
|
|
enum omap_overlay_caps caps, u8 global_alpha)
|
|
{
|
|
static const unsigned shifts[] = { 0, 8, 16, 24, };
|
|
int shift;
|
|
|
|
if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
|
|
return;
|
|
|
|
shift = shifts[plane];
|
|
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
|
|
}
|
|
|
|
static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
|
|
}
|
|
|
|
static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
|
|
}
|
|
|
|
static void dispc_ovl_set_color_mode(enum omap_plane plane,
|
|
enum omap_color_mode color_mode)
|
|
{
|
|
u32 m = 0;
|
|
if (plane != OMAP_DSS_GFX) {
|
|
switch (color_mode) {
|
|
case OMAP_DSS_COLOR_NV12:
|
|
m = 0x0; break;
|
|
case OMAP_DSS_COLOR_RGBX16:
|
|
m = 0x1; break;
|
|
case OMAP_DSS_COLOR_RGBA16:
|
|
m = 0x2; break;
|
|
case OMAP_DSS_COLOR_RGB12U:
|
|
m = 0x4; break;
|
|
case OMAP_DSS_COLOR_ARGB16:
|
|
m = 0x5; break;
|
|
case OMAP_DSS_COLOR_RGB16:
|
|
m = 0x6; break;
|
|
case OMAP_DSS_COLOR_ARGB16_1555:
|
|
m = 0x7; break;
|
|
case OMAP_DSS_COLOR_RGB24U:
|
|
m = 0x8; break;
|
|
case OMAP_DSS_COLOR_RGB24P:
|
|
m = 0x9; break;
|
|
case OMAP_DSS_COLOR_YUV2:
|
|
m = 0xa; break;
|
|
case OMAP_DSS_COLOR_UYVY:
|
|
m = 0xb; break;
|
|
case OMAP_DSS_COLOR_ARGB32:
|
|
m = 0xc; break;
|
|
case OMAP_DSS_COLOR_RGBA32:
|
|
m = 0xd; break;
|
|
case OMAP_DSS_COLOR_RGBX32:
|
|
m = 0xe; break;
|
|
case OMAP_DSS_COLOR_XRGB16_1555:
|
|
m = 0xf; break;
|
|
default:
|
|
BUG(); return;
|
|
}
|
|
} else {
|
|
switch (color_mode) {
|
|
case OMAP_DSS_COLOR_CLUT1:
|
|
m = 0x0; break;
|
|
case OMAP_DSS_COLOR_CLUT2:
|
|
m = 0x1; break;
|
|
case OMAP_DSS_COLOR_CLUT4:
|
|
m = 0x2; break;
|
|
case OMAP_DSS_COLOR_CLUT8:
|
|
m = 0x3; break;
|
|
case OMAP_DSS_COLOR_RGB12U:
|
|
m = 0x4; break;
|
|
case OMAP_DSS_COLOR_ARGB16:
|
|
m = 0x5; break;
|
|
case OMAP_DSS_COLOR_RGB16:
|
|
m = 0x6; break;
|
|
case OMAP_DSS_COLOR_ARGB16_1555:
|
|
m = 0x7; break;
|
|
case OMAP_DSS_COLOR_RGB24U:
|
|
m = 0x8; break;
|
|
case OMAP_DSS_COLOR_RGB24P:
|
|
m = 0x9; break;
|
|
case OMAP_DSS_COLOR_RGBX16:
|
|
m = 0xa; break;
|
|
case OMAP_DSS_COLOR_RGBA16:
|
|
m = 0xb; break;
|
|
case OMAP_DSS_COLOR_ARGB32:
|
|
m = 0xc; break;
|
|
case OMAP_DSS_COLOR_RGBA32:
|
|
m = 0xd; break;
|
|
case OMAP_DSS_COLOR_RGBX32:
|
|
m = 0xe; break;
|
|
case OMAP_DSS_COLOR_XRGB16_1555:
|
|
m = 0xf; break;
|
|
default:
|
|
BUG(); return;
|
|
}
|
|
}
|
|
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
|
|
}
|
|
|
|
static void dispc_ovl_configure_burst_type(enum omap_plane plane,
|
|
enum omap_dss_rotation_type rotation_type)
|
|
{
|
|
if (!dss_has_feature(FEAT_BURST_2D))
|
|
return;
|
|
|
|
if (rotation_type == OMAP_DSS_ROT_TILER)
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
|
|
else
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
|
|
}
|
|
|
|
void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
|
|
{
|
|
int shift;
|
|
u32 val;
|
|
int chan = 0, chan2 = 0;
|
|
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
shift = 8;
|
|
break;
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
case OMAP_DSS_VIDEO3:
|
|
shift = 16;
|
|
break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
|
|
if (dss_has_feature(FEAT_MGR_LCD2)) {
|
|
switch (channel) {
|
|
case OMAP_DSS_CHANNEL_LCD:
|
|
chan = 0;
|
|
chan2 = 0;
|
|
break;
|
|
case OMAP_DSS_CHANNEL_DIGIT:
|
|
chan = 1;
|
|
chan2 = 0;
|
|
break;
|
|
case OMAP_DSS_CHANNEL_LCD2:
|
|
chan = 0;
|
|
chan2 = 1;
|
|
break;
|
|
case OMAP_DSS_CHANNEL_LCD3:
|
|
if (dss_has_feature(FEAT_MGR_LCD3)) {
|
|
chan = 0;
|
|
chan2 = 2;
|
|
} else {
|
|
BUG();
|
|
return;
|
|
}
|
|
break;
|
|
case OMAP_DSS_CHANNEL_WB:
|
|
chan = 0;
|
|
chan2 = 3;
|
|
break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
val = FLD_MOD(val, chan, shift, shift);
|
|
val = FLD_MOD(val, chan2, 31, 30);
|
|
} else {
|
|
val = FLD_MOD(val, channel, shift, shift);
|
|
}
|
|
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
|
|
}
|
|
EXPORT_SYMBOL(dispc_ovl_set_channel_out);
|
|
|
|
static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
|
|
{
|
|
int shift;
|
|
u32 val;
|
|
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
shift = 8;
|
|
break;
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
case OMAP_DSS_VIDEO3:
|
|
shift = 16;
|
|
break;
|
|
default:
|
|
BUG();
|
|
return 0;
|
|
}
|
|
|
|
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
|
|
|
|
if (FLD_GET(val, shift, shift) == 1)
|
|
return OMAP_DSS_CHANNEL_DIGIT;
|
|
|
|
if (!dss_has_feature(FEAT_MGR_LCD2))
|
|
return OMAP_DSS_CHANNEL_LCD;
|
|
|
|
switch (FLD_GET(val, 31, 30)) {
|
|
case 0:
|
|
default:
|
|
return OMAP_DSS_CHANNEL_LCD;
|
|
case 1:
|
|
return OMAP_DSS_CHANNEL_LCD2;
|
|
case 2:
|
|
return OMAP_DSS_CHANNEL_LCD3;
|
|
case 3:
|
|
return OMAP_DSS_CHANNEL_WB;
|
|
}
|
|
}
|
|
|
|
static void dispc_ovl_set_burst_size(enum omap_plane plane,
|
|
enum omap_burst_size burst_size)
|
|
{
|
|
static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
|
|
int shift;
|
|
|
|
shift = shifts[plane];
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
|
|
}
|
|
|
|
static void dispc_configure_burst_sizes(void)
|
|
{
|
|
int i;
|
|
const int burst_size = BURST_SIZE_X8;
|
|
|
|
/* Configure burst size always to maximum size */
|
|
for (i = 0; i < dss_feat_get_num_ovls(); ++i)
|
|
dispc_ovl_set_burst_size(i, burst_size);
|
|
if (dispc.feat->has_writeback)
|
|
dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
|
|
}
|
|
|
|
static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
|
|
{
|
|
unsigned unit = dss_feat_get_burst_size_unit();
|
|
/* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
|
|
return unit * 8;
|
|
}
|
|
|
|
void dispc_enable_gamma_table(bool enable)
|
|
{
|
|
/*
|
|
* This is partially implemented to support only disabling of
|
|
* the gamma table.
|
|
*/
|
|
if (enable) {
|
|
DSSWARN("Gamma table enabling for TV not yet supported");
|
|
return;
|
|
}
|
|
|
|
REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
|
|
}
|
|
|
|
static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
|
|
{
|
|
if (channel == OMAP_DSS_CHANNEL_DIGIT)
|
|
return;
|
|
|
|
mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
|
|
}
|
|
|
|
static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
|
|
const struct omap_dss_cpr_coefs *coefs)
|
|
{
|
|
u32 coef_r, coef_g, coef_b;
|
|
|
|
if (!dss_mgr_is_lcd(channel))
|
|
return;
|
|
|
|
coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
|
|
FLD_VAL(coefs->rb, 9, 0);
|
|
coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
|
|
FLD_VAL(coefs->gb, 9, 0);
|
|
coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
|
|
FLD_VAL(coefs->bb, 9, 0);
|
|
|
|
dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
|
|
dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
|
|
dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
|
|
}
|
|
|
|
static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
|
|
{
|
|
u32 val;
|
|
|
|
BUG_ON(plane == OMAP_DSS_GFX);
|
|
|
|
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
|
|
val = FLD_MOD(val, enable, 9, 9);
|
|
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_enable_replication(enum omap_plane plane,
|
|
enum omap_overlay_caps caps, bool enable)
|
|
{
|
|
static const unsigned shifts[] = { 5, 10, 10, 10 };
|
|
int shift;
|
|
|
|
if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
|
|
return;
|
|
|
|
shift = shifts[plane];
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
|
|
}
|
|
|
|
static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
|
|
u16 height)
|
|
{
|
|
u32 val;
|
|
|
|
val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
|
|
FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
|
|
|
|
dispc_write_reg(DISPC_SIZE_MGR(channel), val);
|
|
}
|
|
|
|
static void dispc_init_fifos(void)
|
|
{
|
|
u32 size;
|
|
int fifo;
|
|
u8 start, end;
|
|
u32 unit;
|
|
int i;
|
|
|
|
unit = dss_feat_get_buffer_size_unit();
|
|
|
|
dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
|
|
|
|
for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
|
|
size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
|
|
size *= unit;
|
|
dispc.fifo_size[fifo] = size;
|
|
|
|
/*
|
|
* By default fifos are mapped directly to overlays, fifo 0 to
|
|
* ovl 0, fifo 1 to ovl 1, etc.
|
|
*/
|
|
dispc.fifo_assignment[fifo] = fifo;
|
|
}
|
|
|
|
/*
|
|
* The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
|
|
* causes problems with certain use cases, like using the tiler in 2D
|
|
* mode. The below hack swaps the fifos of GFX and WB planes, thus
|
|
* giving GFX plane a larger fifo. WB but should work fine with a
|
|
* smaller fifo.
|
|
*/
|
|
if (dispc.feat->gfx_fifo_workaround) {
|
|
u32 v;
|
|
|
|
v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
|
|
|
|
v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
|
|
v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
|
|
v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
|
|
v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
|
|
|
|
dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
|
|
|
|
dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
|
|
dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
|
|
}
|
|
|
|
/*
|
|
* Setup default fifo thresholds.
|
|
*/
|
|
for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
|
|
u32 low, high;
|
|
const bool use_fifomerge = false;
|
|
const bool manual_update = false;
|
|
|
|
dispc_ovl_compute_fifo_thresholds(i, &low, &high,
|
|
use_fifomerge, manual_update);
|
|
|
|
dispc_ovl_set_fifo_threshold(i, low, high);
|
|
}
|
|
|
|
if (dispc.feat->has_writeback) {
|
|
u32 low, high;
|
|
const bool use_fifomerge = false;
|
|
const bool manual_update = false;
|
|
|
|
dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
|
|
use_fifomerge, manual_update);
|
|
|
|
dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
|
|
}
|
|
}
|
|
|
|
static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
|
|
{
|
|
int fifo;
|
|
u32 size = 0;
|
|
|
|
for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
|
|
if (dispc.fifo_assignment[fifo] == plane)
|
|
size += dispc.fifo_size[fifo];
|
|
}
|
|
|
|
return size;
|
|
}
|
|
|
|
void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
|
|
{
|
|
u8 hi_start, hi_end, lo_start, lo_end;
|
|
u32 unit;
|
|
|
|
unit = dss_feat_get_buffer_size_unit();
|
|
|
|
WARN_ON(low % unit != 0);
|
|
WARN_ON(high % unit != 0);
|
|
|
|
low /= unit;
|
|
high /= unit;
|
|
|
|
dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
|
|
dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
|
|
|
|
DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
|
|
plane,
|
|
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
|
|
lo_start, lo_end) * unit,
|
|
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
|
|
hi_start, hi_end) * unit,
|
|
low * unit, high * unit);
|
|
|
|
dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
|
|
FLD_VAL(high, hi_start, hi_end) |
|
|
FLD_VAL(low, lo_start, lo_end));
|
|
|
|
/*
|
|
* configure the preload to the pipeline's high threhold, if HT it's too
|
|
* large for the preload field, set the threshold to the maximum value
|
|
* that can be held by the preload register
|
|
*/
|
|
if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
|
|
plane != OMAP_DSS_WB)
|
|
dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
|
|
}
|
|
|
|
void dispc_enable_fifomerge(bool enable)
|
|
{
|
|
if (!dss_has_feature(FEAT_FIFO_MERGE)) {
|
|
WARN_ON(enable);
|
|
return;
|
|
}
|
|
|
|
DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
|
|
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
|
|
}
|
|
|
|
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
|
|
u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
|
|
bool manual_update)
|
|
{
|
|
/*
|
|
* All sizes are in bytes. Both the buffer and burst are made of
|
|
* buffer_units, and the fifo thresholds must be buffer_unit aligned.
|
|
*/
|
|
|
|
unsigned buf_unit = dss_feat_get_buffer_size_unit();
|
|
unsigned ovl_fifo_size, total_fifo_size, burst_size;
|
|
int i;
|
|
|
|
burst_size = dispc_ovl_get_burst_size(plane);
|
|
ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
|
|
|
|
if (use_fifomerge) {
|
|
total_fifo_size = 0;
|
|
for (i = 0; i < dss_feat_get_num_ovls(); ++i)
|
|
total_fifo_size += dispc_ovl_get_fifo_size(i);
|
|
} else {
|
|
total_fifo_size = ovl_fifo_size;
|
|
}
|
|
|
|
/*
|
|
* We use the same low threshold for both fifomerge and non-fifomerge
|
|
* cases, but for fifomerge we calculate the high threshold using the
|
|
* combined fifo size
|
|
*/
|
|
|
|
if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
|
|
*fifo_low = ovl_fifo_size - burst_size * 2;
|
|
*fifo_high = total_fifo_size - burst_size;
|
|
} else if (plane == OMAP_DSS_WB) {
|
|
/*
|
|
* Most optimal configuration for writeback is to push out data
|
|
* to the interconnect the moment writeback pushes enough pixels
|
|
* in the FIFO to form a burst
|
|
*/
|
|
*fifo_low = 0;
|
|
*fifo_high = burst_size;
|
|
} else {
|
|
*fifo_low = ovl_fifo_size - burst_size;
|
|
*fifo_high = total_fifo_size - buf_unit;
|
|
}
|
|
}
|
|
|
|
static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
|
|
{
|
|
int bit;
|
|
|
|
if (plane == OMAP_DSS_GFX)
|
|
bit = 14;
|
|
else
|
|
bit = 23;
|
|
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
|
|
}
|
|
|
|
static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
|
|
int low, int high)
|
|
{
|
|
dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
|
|
FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
|
|
}
|
|
|
|
static void dispc_init_mflag(void)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* HACK: NV12 color format and MFLAG seem to have problems working
|
|
* together: using two displays, and having an NV12 overlay on one of
|
|
* the displays will cause underflows/synclosts when MFLAG_CTRL=2.
|
|
* Changing MFLAG thresholds and PRELOAD to certain values seem to
|
|
* remove the errors, but there doesn't seem to be a clear logic on
|
|
* which values work and which not.
|
|
*
|
|
* As a work-around, set force MFLAG to always on.
|
|
*/
|
|
dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
|
|
(1 << 0) | /* MFLAG_CTRL = force always on */
|
|
(0 << 2)); /* MFLAG_START = disable */
|
|
|
|
for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
|
|
u32 size = dispc_ovl_get_fifo_size(i);
|
|
u32 unit = dss_feat_get_buffer_size_unit();
|
|
u32 low, high;
|
|
|
|
dispc_ovl_set_mflag(i, true);
|
|
|
|
/*
|
|
* Simulation team suggests below thesholds:
|
|
* HT = fifosize * 5 / 8;
|
|
* LT = fifosize * 4 / 8;
|
|
*/
|
|
|
|
low = size * 4 / 8 / unit;
|
|
high = size * 5 / 8 / unit;
|
|
|
|
dispc_ovl_set_mflag_threshold(i, low, high);
|
|
}
|
|
|
|
if (dispc.feat->has_writeback) {
|
|
u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
|
|
u32 unit = dss_feat_get_buffer_size_unit();
|
|
u32 low, high;
|
|
|
|
dispc_ovl_set_mflag(OMAP_DSS_WB, true);
|
|
|
|
/*
|
|
* Simulation team suggests below thesholds:
|
|
* HT = fifosize * 5 / 8;
|
|
* LT = fifosize * 4 / 8;
|
|
*/
|
|
|
|
low = size * 4 / 8 / unit;
|
|
high = size * 5 / 8 / unit;
|
|
|
|
dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
|
|
}
|
|
}
|
|
|
|
static void dispc_ovl_set_fir(enum omap_plane plane,
|
|
int hinc, int vinc,
|
|
enum omap_color_component color_comp)
|
|
{
|
|
u32 val;
|
|
|
|
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
|
|
u8 hinc_start, hinc_end, vinc_start, vinc_end;
|
|
|
|
dss_feat_get_reg_field(FEAT_REG_FIRHINC,
|
|
&hinc_start, &hinc_end);
|
|
dss_feat_get_reg_field(FEAT_REG_FIRVINC,
|
|
&vinc_start, &vinc_end);
|
|
val = FLD_VAL(vinc, vinc_start, vinc_end) |
|
|
FLD_VAL(hinc, hinc_start, hinc_end);
|
|
|
|
dispc_write_reg(DISPC_OVL_FIR(plane), val);
|
|
} else {
|
|
val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
|
|
dispc_write_reg(DISPC_OVL_FIR2(plane), val);
|
|
}
|
|
}
|
|
|
|
static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
|
|
{
|
|
u32 val;
|
|
u8 hor_start, hor_end, vert_start, vert_end;
|
|
|
|
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
|
|
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
|
|
|
|
val = FLD_VAL(vaccu, vert_start, vert_end) |
|
|
FLD_VAL(haccu, hor_start, hor_end);
|
|
|
|
dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
|
|
{
|
|
u32 val;
|
|
u8 hor_start, hor_end, vert_start, vert_end;
|
|
|
|
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
|
|
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
|
|
|
|
val = FLD_VAL(vaccu, vert_start, vert_end) |
|
|
FLD_VAL(haccu, hor_start, hor_end);
|
|
|
|
dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
|
|
int vaccu)
|
|
{
|
|
u32 val;
|
|
|
|
val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
|
|
dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
|
|
int vaccu)
|
|
{
|
|
u32 val;
|
|
|
|
val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
|
|
dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
|
|
}
|
|
|
|
static void dispc_ovl_set_scale_param(enum omap_plane plane,
|
|
u16 orig_width, u16 orig_height,
|
|
u16 out_width, u16 out_height,
|
|
bool five_taps, u8 rotation,
|
|
enum omap_color_component color_comp)
|
|
{
|
|
int fir_hinc, fir_vinc;
|
|
|
|
fir_hinc = 1024 * orig_width / out_width;
|
|
fir_vinc = 1024 * orig_height / out_height;
|
|
|
|
dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
|
|
color_comp);
|
|
dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
|
|
}
|
|
|
|
static void dispc_ovl_set_accu_uv(enum omap_plane plane,
|
|
u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
|
|
bool ilace, enum omap_color_mode color_mode, u8 rotation)
|
|
{
|
|
int h_accu2_0, h_accu2_1;
|
|
int v_accu2_0, v_accu2_1;
|
|
int chroma_hinc, chroma_vinc;
|
|
int idx;
|
|
|
|
struct accu {
|
|
s8 h0_m, h0_n;
|
|
s8 h1_m, h1_n;
|
|
s8 v0_m, v0_n;
|
|
s8 v1_m, v1_n;
|
|
};
|
|
|
|
const struct accu *accu_table;
|
|
const struct accu *accu_val;
|
|
|
|
static const struct accu accu_nv12[4] = {
|
|
{ 0, 1, 0, 1 , -1, 2, 0, 1 },
|
|
{ 1, 2, -3, 4 , 0, 1, 0, 1 },
|
|
{ -1, 1, 0, 1 , -1, 2, 0, 1 },
|
|
{ -1, 2, -1, 2 , -1, 1, 0, 1 },
|
|
};
|
|
|
|
static const struct accu accu_nv12_ilace[4] = {
|
|
{ 0, 1, 0, 1 , -3, 4, -1, 4 },
|
|
{ -1, 4, -3, 4 , 0, 1, 0, 1 },
|
|
{ -1, 1, 0, 1 , -1, 4, -3, 4 },
|
|
{ -3, 4, -3, 4 , -1, 1, 0, 1 },
|
|
};
|
|
|
|
static const struct accu accu_yuv[4] = {
|
|
{ 0, 1, 0, 1, 0, 1, 0, 1 },
|
|
{ 0, 1, 0, 1, 0, 1, 0, 1 },
|
|
{ -1, 1, 0, 1, 0, 1, 0, 1 },
|
|
{ 0, 1, 0, 1, -1, 1, 0, 1 },
|
|
};
|
|
|
|
switch (rotation) {
|
|
case OMAP_DSS_ROT_0:
|
|
idx = 0;
|
|
break;
|
|
case OMAP_DSS_ROT_90:
|
|
idx = 1;
|
|
break;
|
|
case OMAP_DSS_ROT_180:
|
|
idx = 2;
|
|
break;
|
|
case OMAP_DSS_ROT_270:
|
|
idx = 3;
|
|
break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
switch (color_mode) {
|
|
case OMAP_DSS_COLOR_NV12:
|
|
if (ilace)
|
|
accu_table = accu_nv12_ilace;
|
|
else
|
|
accu_table = accu_nv12;
|
|
break;
|
|
case OMAP_DSS_COLOR_YUV2:
|
|
case OMAP_DSS_COLOR_UYVY:
|
|
accu_table = accu_yuv;
|
|
break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
accu_val = &accu_table[idx];
|
|
|
|
chroma_hinc = 1024 * orig_width / out_width;
|
|
chroma_vinc = 1024 * orig_height / out_height;
|
|
|
|
h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
|
|
h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
|
|
v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
|
|
v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
|
|
|
|
dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
|
|
dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
|
|
}
|
|
|
|
static void dispc_ovl_set_scaling_common(enum omap_plane plane,
|
|
u16 orig_width, u16 orig_height,
|
|
u16 out_width, u16 out_height,
|
|
bool ilace, bool five_taps,
|
|
bool fieldmode, enum omap_color_mode color_mode,
|
|
u8 rotation)
|
|
{
|
|
int accu0 = 0;
|
|
int accu1 = 0;
|
|
u32 l;
|
|
|
|
dispc_ovl_set_scale_param(plane, orig_width, orig_height,
|
|
out_width, out_height, five_taps,
|
|
rotation, DISPC_COLOR_COMPONENT_RGB_Y);
|
|
l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
|
|
|
|
/* RESIZEENABLE and VERTICALTAPS */
|
|
l &= ~((0x3 << 5) | (0x1 << 21));
|
|
l |= (orig_width != out_width) ? (1 << 5) : 0;
|
|
l |= (orig_height != out_height) ? (1 << 6) : 0;
|
|
l |= five_taps ? (1 << 21) : 0;
|
|
|
|
/* VRESIZECONF and HRESIZECONF */
|
|
if (dss_has_feature(FEAT_RESIZECONF)) {
|
|
l &= ~(0x3 << 7);
|
|
l |= (orig_width <= out_width) ? 0 : (1 << 7);
|
|
l |= (orig_height <= out_height) ? 0 : (1 << 8);
|
|
}
|
|
|
|
/* LINEBUFFERSPLIT */
|
|
if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
|
|
l &= ~(0x1 << 22);
|
|
l |= five_taps ? (1 << 22) : 0;
|
|
}
|
|
|
|
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
|
|
|
|
/*
|
|
* field 0 = even field = bottom field
|
|
* field 1 = odd field = top field
|
|
*/
|
|
if (ilace && !fieldmode) {
|
|
accu1 = 0;
|
|
accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
|
|
if (accu0 >= 1024/2) {
|
|
accu1 = 1024/2;
|
|
accu0 -= accu1;
|
|
}
|
|
}
|
|
|
|
dispc_ovl_set_vid_accu0(plane, 0, accu0);
|
|
dispc_ovl_set_vid_accu1(plane, 0, accu1);
|
|
}
|
|
|
|
static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
|
|
u16 orig_width, u16 orig_height,
|
|
u16 out_width, u16 out_height,
|
|
bool ilace, bool five_taps,
|
|
bool fieldmode, enum omap_color_mode color_mode,
|
|
u8 rotation)
|
|
{
|
|
int scale_x = out_width != orig_width;
|
|
int scale_y = out_height != orig_height;
|
|
bool chroma_upscale = plane != OMAP_DSS_WB;
|
|
|
|
if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
|
|
return;
|
|
if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
|
|
color_mode != OMAP_DSS_COLOR_UYVY &&
|
|
color_mode != OMAP_DSS_COLOR_NV12)) {
|
|
/* reset chroma resampling for RGB formats */
|
|
if (plane != OMAP_DSS_WB)
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
|
|
return;
|
|
}
|
|
|
|
dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
|
|
out_height, ilace, color_mode, rotation);
|
|
|
|
switch (color_mode) {
|
|
case OMAP_DSS_COLOR_NV12:
|
|
if (chroma_upscale) {
|
|
/* UV is subsampled by 2 horizontally and vertically */
|
|
orig_height >>= 1;
|
|
orig_width >>= 1;
|
|
} else {
|
|
/* UV is downsampled by 2 horizontally and vertically */
|
|
orig_height <<= 1;
|
|
orig_width <<= 1;
|
|
}
|
|
|
|
break;
|
|
case OMAP_DSS_COLOR_YUV2:
|
|
case OMAP_DSS_COLOR_UYVY:
|
|
/* For YUV422 with 90/270 rotation, we don't upsample chroma */
|
|
if (rotation == OMAP_DSS_ROT_0 ||
|
|
rotation == OMAP_DSS_ROT_180) {
|
|
if (chroma_upscale)
|
|
/* UV is subsampled by 2 horizontally */
|
|
orig_width >>= 1;
|
|
else
|
|
/* UV is downsampled by 2 horizontally */
|
|
orig_width <<= 1;
|
|
}
|
|
|
|
/* must use FIR for YUV422 if rotated */
|
|
if (rotation != OMAP_DSS_ROT_0)
|
|
scale_x = scale_y = true;
|
|
|
|
break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
if (out_width != orig_width)
|
|
scale_x = true;
|
|
if (out_height != orig_height)
|
|
scale_y = true;
|
|
|
|
dispc_ovl_set_scale_param(plane, orig_width, orig_height,
|
|
out_width, out_height, five_taps,
|
|
rotation, DISPC_COLOR_COMPONENT_UV);
|
|
|
|
if (plane != OMAP_DSS_WB)
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
|
|
(scale_x || scale_y) ? 1 : 0, 8, 8);
|
|
|
|
/* set H scaling */
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
|
|
/* set V scaling */
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
|
|
}
|
|
|
|
static void dispc_ovl_set_scaling(enum omap_plane plane,
|
|
u16 orig_width, u16 orig_height,
|
|
u16 out_width, u16 out_height,
|
|
bool ilace, bool five_taps,
|
|
bool fieldmode, enum omap_color_mode color_mode,
|
|
u8 rotation)
|
|
{
|
|
BUG_ON(plane == OMAP_DSS_GFX);
|
|
|
|
dispc_ovl_set_scaling_common(plane,
|
|
orig_width, orig_height,
|
|
out_width, out_height,
|
|
ilace, five_taps,
|
|
fieldmode, color_mode,
|
|
rotation);
|
|
|
|
dispc_ovl_set_scaling_uv(plane,
|
|
orig_width, orig_height,
|
|
out_width, out_height,
|
|
ilace, five_taps,
|
|
fieldmode, color_mode,
|
|
rotation);
|
|
}
|
|
|
|
static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
|
|
enum omap_dss_rotation_type rotation_type,
|
|
bool mirroring, enum omap_color_mode color_mode)
|
|
{
|
|
bool row_repeat = false;
|
|
int vidrot = 0;
|
|
|
|
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
|
|
color_mode == OMAP_DSS_COLOR_UYVY) {
|
|
|
|
if (mirroring) {
|
|
switch (rotation) {
|
|
case OMAP_DSS_ROT_0:
|
|
vidrot = 2;
|
|
break;
|
|
case OMAP_DSS_ROT_90:
|
|
vidrot = 1;
|
|
break;
|
|
case OMAP_DSS_ROT_180:
|
|
vidrot = 0;
|
|
break;
|
|
case OMAP_DSS_ROT_270:
|
|
vidrot = 3;
|
|
break;
|
|
}
|
|
} else {
|
|
switch (rotation) {
|
|
case OMAP_DSS_ROT_0:
|
|
vidrot = 0;
|
|
break;
|
|
case OMAP_DSS_ROT_90:
|
|
vidrot = 1;
|
|
break;
|
|
case OMAP_DSS_ROT_180:
|
|
vidrot = 2;
|
|
break;
|
|
case OMAP_DSS_ROT_270:
|
|
vidrot = 3;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
|
|
row_repeat = true;
|
|
else
|
|
row_repeat = false;
|
|
}
|
|
|
|
/*
|
|
* OMAP4/5 Errata i631:
|
|
* NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
|
|
* rows beyond the framebuffer, which may cause OCP error.
|
|
*/
|
|
if (color_mode == OMAP_DSS_COLOR_NV12 &&
|
|
rotation_type != OMAP_DSS_ROT_TILER)
|
|
vidrot = 1;
|
|
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
|
|
if (dss_has_feature(FEAT_ROWREPEATENABLE))
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
|
|
row_repeat ? 1 : 0, 18, 18);
|
|
|
|
if (color_mode == OMAP_DSS_COLOR_NV12) {
|
|
bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
|
|
(rotation == OMAP_DSS_ROT_0 ||
|
|
rotation == OMAP_DSS_ROT_180);
|
|
/* DOUBLESTRIDE */
|
|
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
|
|
}
|
|
|
|
}
|
|
|
|
static int color_mode_to_bpp(enum omap_color_mode color_mode)
|
|
{
|
|
switch (color_mode) {
|
|
case OMAP_DSS_COLOR_CLUT1:
|
|
return 1;
|
|
case OMAP_DSS_COLOR_CLUT2:
|
|
return 2;
|
|
case OMAP_DSS_COLOR_CLUT4:
|
|
return 4;
|
|
case OMAP_DSS_COLOR_CLUT8:
|
|
case OMAP_DSS_COLOR_NV12:
|
|
return 8;
|
|
case OMAP_DSS_COLOR_RGB12U:
|
|
case OMAP_DSS_COLOR_RGB16:
|
|
case OMAP_DSS_COLOR_ARGB16:
|
|
case OMAP_DSS_COLOR_YUV2:
|
|
case OMAP_DSS_COLOR_UYVY:
|
|
case OMAP_DSS_COLOR_RGBA16:
|
|
case OMAP_DSS_COLOR_RGBX16:
|
|
case OMAP_DSS_COLOR_ARGB16_1555:
|
|
case OMAP_DSS_COLOR_XRGB16_1555:
|
|
return 16;
|
|
case OMAP_DSS_COLOR_RGB24P:
|
|
return 24;
|
|
case OMAP_DSS_COLOR_RGB24U:
|
|
case OMAP_DSS_COLOR_ARGB32:
|
|
case OMAP_DSS_COLOR_RGBA32:
|
|
case OMAP_DSS_COLOR_RGBX32:
|
|
return 32;
|
|
default:
|
|
BUG();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static s32 pixinc(int pixels, u8 ps)
|
|
{
|
|
if (pixels == 1)
|
|
return 1;
|
|
else if (pixels > 1)
|
|
return 1 + (pixels - 1) * ps;
|
|
else if (pixels < 0)
|
|
return 1 - (-pixels + 1) * ps;
|
|
else
|
|
BUG();
|
|
return 0;
|
|
}
|
|
|
|
static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
|
|
u16 screen_width,
|
|
u16 width, u16 height,
|
|
enum omap_color_mode color_mode, bool fieldmode,
|
|
unsigned int field_offset,
|
|
unsigned *offset0, unsigned *offset1,
|
|
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
|
|
{
|
|
u8 ps;
|
|
|
|
/* FIXME CLUT formats */
|
|
switch (color_mode) {
|
|
case OMAP_DSS_COLOR_CLUT1:
|
|
case OMAP_DSS_COLOR_CLUT2:
|
|
case OMAP_DSS_COLOR_CLUT4:
|
|
case OMAP_DSS_COLOR_CLUT8:
|
|
BUG();
|
|
return;
|
|
case OMAP_DSS_COLOR_YUV2:
|
|
case OMAP_DSS_COLOR_UYVY:
|
|
ps = 4;
|
|
break;
|
|
default:
|
|
ps = color_mode_to_bpp(color_mode) / 8;
|
|
break;
|
|
}
|
|
|
|
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
|
|
width, height);
|
|
|
|
/*
|
|
* field 0 = even field = bottom field
|
|
* field 1 = odd field = top field
|
|
*/
|
|
switch (rotation + mirror * 4) {
|
|
case OMAP_DSS_ROT_0:
|
|
case OMAP_DSS_ROT_180:
|
|
/*
|
|
* If the pixel format is YUV or UYVY divide the width
|
|
* of the image by 2 for 0 and 180 degree rotation.
|
|
*/
|
|
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
|
|
color_mode == OMAP_DSS_COLOR_UYVY)
|
|
width = width >> 1;
|
|
fallthrough;
|
|
case OMAP_DSS_ROT_90:
|
|
case OMAP_DSS_ROT_270:
|
|
*offset1 = 0;
|
|
if (field_offset)
|
|
*offset0 = field_offset * screen_width * ps;
|
|
else
|
|
*offset0 = 0;
|
|
|
|
*row_inc = pixinc(1 +
|
|
(y_predecim * screen_width - x_predecim * width) +
|
|
(fieldmode ? screen_width : 0), ps);
|
|
*pix_inc = pixinc(x_predecim, ps);
|
|
break;
|
|
|
|
case OMAP_DSS_ROT_0 + 4:
|
|
case OMAP_DSS_ROT_180 + 4:
|
|
/* If the pixel format is YUV or UYVY divide the width
|
|
* of the image by 2 for 0 degree and 180 degree
|
|
*/
|
|
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
|
|
color_mode == OMAP_DSS_COLOR_UYVY)
|
|
width = width >> 1;
|
|
fallthrough;
|
|
case OMAP_DSS_ROT_90 + 4:
|
|
case OMAP_DSS_ROT_270 + 4:
|
|
*offset1 = 0;
|
|
if (field_offset)
|
|
*offset0 = field_offset * screen_width * ps;
|
|
else
|
|
*offset0 = 0;
|
|
*row_inc = pixinc(1 -
|
|
(y_predecim * screen_width + x_predecim * width) -
|
|
(fieldmode ? screen_width : 0), ps);
|
|
*pix_inc = pixinc(x_predecim, ps);
|
|
break;
|
|
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
}
|
|
|
|
static void calc_dma_rotation_offset(u8 rotation, bool mirror,
|
|
u16 screen_width,
|
|
u16 width, u16 height,
|
|
enum omap_color_mode color_mode, bool fieldmode,
|
|
unsigned int field_offset,
|
|
unsigned *offset0, unsigned *offset1,
|
|
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
|
|
{
|
|
u8 ps;
|
|
u16 fbw, fbh;
|
|
|
|
/* FIXME CLUT formats */
|
|
switch (color_mode) {
|
|
case OMAP_DSS_COLOR_CLUT1:
|
|
case OMAP_DSS_COLOR_CLUT2:
|
|
case OMAP_DSS_COLOR_CLUT4:
|
|
case OMAP_DSS_COLOR_CLUT8:
|
|
BUG();
|
|
return;
|
|
default:
|
|
ps = color_mode_to_bpp(color_mode) / 8;
|
|
break;
|
|
}
|
|
|
|
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
|
|
width, height);
|
|
|
|
/* width & height are overlay sizes, convert to fb sizes */
|
|
|
|
if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
|
|
fbw = width;
|
|
fbh = height;
|
|
} else {
|
|
fbw = height;
|
|
fbh = width;
|
|
}
|
|
|
|
/*
|
|
* field 0 = even field = bottom field
|
|
* field 1 = odd field = top field
|
|
*/
|
|
switch (rotation + mirror * 4) {
|
|
case OMAP_DSS_ROT_0:
|
|
*offset1 = 0;
|
|
if (field_offset)
|
|
*offset0 = *offset1 + field_offset * screen_width * ps;
|
|
else
|
|
*offset0 = *offset1;
|
|
*row_inc = pixinc(1 +
|
|
(y_predecim * screen_width - fbw * x_predecim) +
|
|
(fieldmode ? screen_width : 0), ps);
|
|
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
|
|
color_mode == OMAP_DSS_COLOR_UYVY)
|
|
*pix_inc = pixinc(x_predecim, 2 * ps);
|
|
else
|
|
*pix_inc = pixinc(x_predecim, ps);
|
|
break;
|
|
case OMAP_DSS_ROT_90:
|
|
*offset1 = screen_width * (fbh - 1) * ps;
|
|
if (field_offset)
|
|
*offset0 = *offset1 + field_offset * ps;
|
|
else
|
|
*offset0 = *offset1;
|
|
*row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
|
|
y_predecim + (fieldmode ? 1 : 0), ps);
|
|
*pix_inc = pixinc(-x_predecim * screen_width, ps);
|
|
break;
|
|
case OMAP_DSS_ROT_180:
|
|
*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
|
|
if (field_offset)
|
|
*offset0 = *offset1 - field_offset * screen_width * ps;
|
|
else
|
|
*offset0 = *offset1;
|
|
*row_inc = pixinc(-1 -
|
|
(y_predecim * screen_width - fbw * x_predecim) -
|
|
(fieldmode ? screen_width : 0), ps);
|
|
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
|
|
color_mode == OMAP_DSS_COLOR_UYVY)
|
|
*pix_inc = pixinc(-x_predecim, 2 * ps);
|
|
else
|
|
*pix_inc = pixinc(-x_predecim, ps);
|
|
break;
|
|
case OMAP_DSS_ROT_270:
|
|
*offset1 = (fbw - 1) * ps;
|
|
if (field_offset)
|
|
*offset0 = *offset1 - field_offset * ps;
|
|
else
|
|
*offset0 = *offset1;
|
|
*row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
|
|
y_predecim - (fieldmode ? 1 : 0), ps);
|
|
*pix_inc = pixinc(x_predecim * screen_width, ps);
|
|
break;
|
|
|
|
/* mirroring */
|
|
case OMAP_DSS_ROT_0 + 4:
|
|
*offset1 = (fbw - 1) * ps;
|
|
if (field_offset)
|
|
*offset0 = *offset1 + field_offset * screen_width * ps;
|
|
else
|
|
*offset0 = *offset1;
|
|
*row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
|
|
(fieldmode ? screen_width : 0),
|
|
ps);
|
|
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
|
|
color_mode == OMAP_DSS_COLOR_UYVY)
|
|
*pix_inc = pixinc(-x_predecim, 2 * ps);
|
|
else
|
|
*pix_inc = pixinc(-x_predecim, ps);
|
|
break;
|
|
|
|
case OMAP_DSS_ROT_90 + 4:
|
|
*offset1 = 0;
|
|
if (field_offset)
|
|
*offset0 = *offset1 + field_offset * ps;
|
|
else
|
|
*offset0 = *offset1;
|
|
*row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
|
|
y_predecim + (fieldmode ? 1 : 0),
|
|
ps);
|
|
*pix_inc = pixinc(x_predecim * screen_width, ps);
|
|
break;
|
|
|
|
case OMAP_DSS_ROT_180 + 4:
|
|
*offset1 = screen_width * (fbh - 1) * ps;
|
|
if (field_offset)
|
|
*offset0 = *offset1 - field_offset * screen_width * ps;
|
|
else
|
|
*offset0 = *offset1;
|
|
*row_inc = pixinc(1 - y_predecim |