66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a77961 CPG Core Clocks */
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#define R8A77961_CLK_Z 0
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#define R8A77961_CLK_Z2 1
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#define R8A77961_CLK_ZR 2
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#define R8A77961_CLK_ZG 3
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#define R8A77961_CLK_ZTR 4
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#define R8A77961_CLK_ZTRD2 5
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#define R8A77961_CLK_ZT 6
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#define R8A77961_CLK_ZX 7
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#define R8A77961_CLK_S0D1 8
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#define R8A77961_CLK_S0D2 9
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#define R8A77961_CLK_S0D3 10
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#define R8A77961_CLK_S0D4 11
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#define R8A77961_CLK_S0D6 12
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#define R8A77961_CLK_S0D8 13
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#define R8A77961_CLK_S0D12 14
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#define R8A77961_CLK_S1D1 15
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#define R8A77961_CLK_S1D2 16
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#define R8A77961_CLK_S1D4 17
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#define R8A77961_CLK_S2D1 18
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#define R8A77961_CLK_S2D2 19
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#define R8A77961_CLK_S2D4 20
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#define R8A77961_CLK_S3D1 21
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#define R8A77961_CLK_S3D2 22
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#define R8A77961_CLK_S3D4 23
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#define R8A77961_CLK_LB 24
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#define R8A77961_CLK_CL 25
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#define R8A77961_CLK_ZB3 26
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#define R8A77961_CLK_ZB3D2 27
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#define R8A77961_CLK_ZB3D4 28
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#define R8A77961_CLK_CR 29
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#define R8A77961_CLK_CRD2 30
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#define R8A77961_CLK_SD0H 31
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#define R8A77961_CLK_SD0 32
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#define R8A77961_CLK_SD1H 33
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#define R8A77961_CLK_SD1 34
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#define R8A77961_CLK_SD2H 35
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#define R8A77961_CLK_SD2 36
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#define R8A77961_CLK_SD3H 37
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#define R8A77961_CLK_SD3 38
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#define R8A77961_CLK_SSP2 39
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#define R8A77961_CLK_SSP1 40
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#define R8A77961_CLK_SSPRS 41
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#define R8A77961_CLK_RPC 42
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#define R8A77961_CLK_RPCD2 43
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#define R8A77961_CLK_MSO 44
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#define R8A77961_CLK_CANFD 45
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#define R8A77961_CLK_HDMI 46
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#define R8A77961_CLK_CSI0 47
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/* CLK_CSIREF was removed */
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#define R8A77961_CLK_CP 49
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#define R8A77961_CLK_CPEX 50
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#define R8A77961_CLK_R 51
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#define R8A77961_CLK_OSC 52
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#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
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