144 lines
4.9 KiB
C
144 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_ARCH_OMAP_IO_H
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#define __ASM_ARCH_OMAP_IO_H
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#ifndef __ASSEMBLER__
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#include <linux/types.h>
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#ifdef CONFIG_ARCH_OMAP1
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/*
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* NOTE: Please use ioremap + __raw_read/write where possible instead of these
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*/
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extern u8 omap_readb(u32 pa);
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extern u16 omap_readw(u32 pa);
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extern u32 omap_readl(u32 pa);
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extern void omap_writeb(u8 v, u32 pa);
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extern void omap_writew(u16 v, u32 pa);
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extern void omap_writel(u32 v, u32 pa);
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#elif defined(CONFIG_COMPILE_TEST)
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static inline u8 omap_readb(u32 pa) { return 0; }
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static inline u16 omap_readw(u32 pa) { return 0; }
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static inline u32 omap_readl(u32 pa) { return 0; }
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static inline void omap_writeb(u8 v, u32 pa) { }
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static inline void omap_writew(u16 v, u32 pa) { }
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static inline void omap_writel(u32 v, u32 pa) { }
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#endif
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#endif
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/*
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* ----------------------------------------------------------------------------
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* System control registers
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* ----------------------------------------------------------------------------
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*/
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#define MOD_CONF_CTRL_0 0xfffe1080
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#define MOD_CONF_CTRL_1 0xfffe1110
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/*
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* ---------------------------------------------------------------------------
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* UPLD
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* ---------------------------------------------------------------------------
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*/
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#define ULPD_REG_BASE (0xfffe0800)
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#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
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#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
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#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
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# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
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# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
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#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
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# define SOFT_UDC_REQ (1 << 4)
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# define SOFT_USB_CLK_REQ (1 << 3)
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# define SOFT_DPLL_REQ (1 << 0)
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#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
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#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
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#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
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#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
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#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
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# define DIS_MMC2_DPLL_REQ (1 << 11)
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# define DIS_MMC1_DPLL_REQ (1 << 10)
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# define DIS_UART3_DPLL_REQ (1 << 9)
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# define DIS_UART2_DPLL_REQ (1 << 8)
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# define DIS_UART1_DPLL_REQ (1 << 7)
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# define DIS_USB_HOST_DPLL_REQ (1 << 6)
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#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
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#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
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/*
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* ----------------------------------------------------------------------------
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* Clocks
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* ----------------------------------------------------------------------------
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*/
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#define CLKGEN_REG_BASE (0xfffece00)
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#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
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#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
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#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
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#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
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#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
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#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
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#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
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#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
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#define CK_RATEF 1
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#define CK_IDLEF 2
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#define CK_ENABLEF 4
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#define CK_SELECTF 8
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#define SETARM_IDLE_SHIFT
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/* DPLL control registers */
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#define DPLL_CTL (0xfffecf00)
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/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
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#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
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#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
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#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
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#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
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#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
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/*
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* ----------------------------------------------------------------------------
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* Pulse-Width Light
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* ----------------------------------------------------------------------------
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*/
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#define OMAP_PWL_BASE 0xfffb5800
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#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
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#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
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/*
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* ----------------------------------------------------------------------------
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* Pin multiplexing registers
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* ----------------------------------------------------------------------------
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*/
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#define FUNC_MUX_CTRL_0 0xfffe1000
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#define FUNC_MUX_CTRL_1 0xfffe1004
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#define FUNC_MUX_CTRL_2 0xfffe1008
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#define COMP_MODE_CTRL_0 0xfffe100c
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#define FUNC_MUX_CTRL_3 0xfffe1010
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#define FUNC_MUX_CTRL_4 0xfffe1014
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#define FUNC_MUX_CTRL_5 0xfffe1018
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#define FUNC_MUX_CTRL_6 0xfffe101C
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#define FUNC_MUX_CTRL_7 0xfffe1020
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#define FUNC_MUX_CTRL_8 0xfffe1024
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#define FUNC_MUX_CTRL_9 0xfffe1028
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#define FUNC_MUX_CTRL_A 0xfffe102C
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#define FUNC_MUX_CTRL_B 0xfffe1030
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#define FUNC_MUX_CTRL_C 0xfffe1034
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#define FUNC_MUX_CTRL_D 0xfffe1038
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#define PULL_DWN_CTRL_0 0xfffe1040
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#define PULL_DWN_CTRL_1 0xfffe1044
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#define PULL_DWN_CTRL_2 0xfffe1048
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#define PULL_DWN_CTRL_3 0xfffe104c
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#define PULL_DWN_CTRL_4 0xfffe10ac
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/* OMAP-1610 specific multiplexing registers */
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#define FUNC_MUX_CTRL_E 0xfffe1090
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#define FUNC_MUX_CTRL_F 0xfffe1094
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#define FUNC_MUX_CTRL_10 0xfffe1098
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#define FUNC_MUX_CTRL_11 0xfffe109c
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#define FUNC_MUX_CTRL_12 0xfffe10a0
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#define PU_PD_SEL_0 0xfffe10b4
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#define PU_PD_SEL_1 0xfffe10b8
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#define PU_PD_SEL_2 0xfffe10bc
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#define PU_PD_SEL_3 0xfffe10c0
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#define PU_PD_SEL_4 0xfffe10c4
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#endif
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