314 lines
8.2 KiB
C
314 lines
8.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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#include <linux/module.h>
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#include <sound/hdaudio_ext.h>
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#include <sound/hda_register.h>
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#include <sound/hda_component.h>
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#include "../ops.h"
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#include "hda.h"
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/*
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* HDA Operations.
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*/
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int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
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{
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unsigned long timeout;
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u32 gctl = 0;
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u32 val;
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/* 0 to enter reset and 1 to exit reset */
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val = reset ? 0 : SOF_HDA_GCTL_RESET;
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/* enter/exit HDA controller reset */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
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SOF_HDA_GCTL_RESET, val);
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/* wait to enter/exit reset */
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timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
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while (time_before(jiffies, timeout)) {
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gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
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if ((gctl & SOF_HDA_GCTL_RESET) == val)
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return 0;
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usleep_range(500, 1000);
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}
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/* enter/exit reset failed */
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dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
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reset ? "reset" : "ready", gctl);
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return -EIO;
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}
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int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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u32 cap, offset, feature;
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int count = 0;
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int ret;
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/*
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* On some devices, one reset cycle is necessary before reading
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* capabilities
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*/
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ret = hda_dsp_ctrl_link_reset(sdev, true);
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if (ret < 0)
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return ret;
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ret = hda_dsp_ctrl_link_reset(sdev, false);
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if (ret < 0)
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return ret;
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offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
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do {
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dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
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offset & SOF_HDA_CAP_NEXT_MASK);
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cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
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if (cap == -1) {
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dev_dbg(bus->dev, "Invalid capability reg read\n");
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break;
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}
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feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF;
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switch (feature) {
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case SOF_HDA_PP_CAP_ID:
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dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
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offset);
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bus->ppcap = bus->remap_addr + offset;
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sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
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break;
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case SOF_HDA_SPIB_CAP_ID:
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dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
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offset);
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bus->spbcap = bus->remap_addr + offset;
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sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
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break;
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case SOF_HDA_DRSM_CAP_ID:
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dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
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offset);
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bus->drsmcap = bus->remap_addr + offset;
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sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
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break;
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case SOF_HDA_GTS_CAP_ID:
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dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
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offset);
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bus->gtscap = bus->remap_addr + offset;
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break;
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case SOF_HDA_ML_CAP_ID:
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dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
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offset);
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bus->mlcap = bus->remap_addr + offset;
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break;
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default:
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dev_dbg(sdev->dev, "found capability %d at 0x%x\n",
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feature, offset);
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break;
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}
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offset = cap & SOF_HDA_CAP_NEXT_MASK;
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} while (count++ <= SOF_HDA_MAX_CAPS && offset);
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return 0;
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}
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void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
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{
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u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0;
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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SOF_HDA_PPCTL_GPROCEN, val);
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}
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void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
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{
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u32 val = enable ? SOF_HDA_PPCTL_PIE : 0;
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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SOF_HDA_PPCTL_PIE, val);
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}
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void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
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{
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u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
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snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
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}
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/*
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* enable/disable audio dsp clock gating and power gating bits.
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* This allows the HW to opportunistically power and clock gate
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* the audio dsp when it is idle
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*/
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int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
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{
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u32 val;
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/* enable/disable audio dsp clock gating */
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val = enable ? PCI_CGCTL_ADSPDCGE : 0;
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snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
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/* enable/disable DMI Link L1 support */
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val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0;
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
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HDA_VS_INTEL_EM2_L1SEN, val);
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/* enable/disable audio dsp power gating */
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val = enable ? 0 : PCI_PGCTL_ADSPPGD;
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snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
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return 0;
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}
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int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_stream *stream;
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int sd_offset, ret = 0;
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if (bus->chip_init)
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return 0;
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hda_codec_set_codec_wakeup(sdev, true);
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hda_dsp_ctrl_misc_clock_gating(sdev, false);
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/* reset HDA controller */
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ret = hda_dsp_ctrl_link_reset(sdev, true);
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to reset HDA controller\n");
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goto err;
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}
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usleep_range(500, 1000);
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/* exit HDA controller reset */
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ret = hda_dsp_ctrl_link_reset(sdev, false);
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
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goto err;
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}
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usleep_range(1000, 1200);
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hda_codec_detect_mask(sdev);
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/* clear stream status */
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list_for_each_entry(stream, &bus->stream_list, list) {
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sd_offset = SOF_STREAM_SD_OFFSET(stream);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_SD_STS,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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}
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/* clear WAKESTS */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
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SOF_HDA_WAKESTS_INT_MASK);
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hda_codec_rirb_status_clear(sdev);
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/* clear interrupt status register */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
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hda_codec_init_cmd_io(sdev);
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/* enable CIE and GIE interrupts */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
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/* program the position buffer */
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if (bus->use_posbuf && bus->posbuf.addr) {
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
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(u32)bus->posbuf.addr);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
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upper_32_bits(bus->posbuf.addr));
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}
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hda_bus_ml_reset_losidv(bus);
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bus->chip_init = true;
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err:
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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hda_codec_set_codec_wakeup(sdev, false);
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return ret;
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}
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void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_stream *stream;
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int sd_offset;
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if (!bus->chip_init)
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return;
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/* disable interrupts in stream descriptor */
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list_for_each_entry(stream, &bus->stream_list, list) {
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sd_offset = SOF_STREAM_SD_OFFSET(stream);
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset +
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SOF_HDA_ADSP_REG_SD_CTL,
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SOF_HDA_CL_DMA_SD_INT_MASK,
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0);
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}
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/* disable SIE for all streams */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_ALL_STREAM, 0);
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/* disable controller CIE and GIE */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
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0);
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/* clear stream status */
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list_for_each_entry(stream, &bus->stream_list, list) {
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sd_offset = SOF_STREAM_SD_OFFSET(stream);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_SD_STS,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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}
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/* clear WAKESTS */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
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SOF_HDA_WAKESTS_INT_MASK);
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hda_codec_rirb_status_clear(sdev);
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/* clear interrupt status register */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
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hda_codec_stop_cmd_io(sdev);
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/* disable position buffer */
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if (bus->use_posbuf && bus->posbuf.addr) {
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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SOF_HDA_ADSP_DPLBASE, 0);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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SOF_HDA_ADSP_DPUBASE, 0);
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}
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bus->chip_init = false;
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}
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