307 lines
8.2 KiB
C
307 lines
8.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#ifndef __UAPI_IVPU_DRM_H__
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#define __UAPI_IVPU_DRM_H__
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define DRM_IVPU_DRIVER_MAJOR 1
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#define DRM_IVPU_DRIVER_MINOR 0
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#define DRM_IVPU_GET_PARAM 0x00
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#define DRM_IVPU_SET_PARAM 0x01
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#define DRM_IVPU_BO_CREATE 0x02
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#define DRM_IVPU_BO_INFO 0x03
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#define DRM_IVPU_SUBMIT 0x05
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#define DRM_IVPU_BO_WAIT 0x06
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#define DRM_IOCTL_IVPU_GET_PARAM \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
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#define DRM_IOCTL_IVPU_SET_PARAM \
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DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
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#define DRM_IOCTL_IVPU_BO_CREATE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create)
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#define DRM_IOCTL_IVPU_BO_INFO \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info)
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#define DRM_IOCTL_IVPU_SUBMIT \
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DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit)
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#define DRM_IOCTL_IVPU_BO_WAIT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)
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/**
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* DOC: contexts
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*
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* VPU contexts have private virtual address space, job queues and priority.
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* Each context is identified by an unique ID. Context is created on open().
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*/
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#define DRM_IVPU_PARAM_DEVICE_ID 0
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#define DRM_IVPU_PARAM_DEVICE_REVISION 1
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#define DRM_IVPU_PARAM_PLATFORM_TYPE 2
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#define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
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#define DRM_IVPU_PARAM_NUM_CONTEXTS 4
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#define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
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#define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6
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#define DRM_IVPU_PARAM_CONTEXT_ID 7
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#define DRM_IVPU_PARAM_FW_API_VERSION 8
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#define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9
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#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
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#define DRM_IVPU_PARAM_TILE_CONFIG 11
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#define DRM_IVPU_PARAM_SKU 12
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#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
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#define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
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#define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
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#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
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#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
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/**
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* struct drm_ivpu_param - Get/Set VPU parameters
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*/
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struct drm_ivpu_param {
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/**
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* @param:
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*
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* Supported params:
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*
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* %DRM_IVPU_PARAM_DEVICE_ID:
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* PCI Device ID of the VPU device (read-only)
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*
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* %DRM_IVPU_PARAM_DEVICE_REVISION:
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* VPU device revision (read-only)
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*
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* %DRM_IVPU_PARAM_PLATFORM_TYPE:
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* Returns %DRM_IVPU_PLATFORM_TYPE_SILICON on real hardware or device specific
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* platform type when executing on a simulator or emulator (read-only)
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*
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* %DRM_IVPU_PARAM_CORE_CLOCK_RATE:
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* Current PLL frequency (read-only)
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*
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* %DRM_IVPU_PARAM_NUM_CONTEXTS:
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* Maximum number of simultaneously existing contexts (read-only)
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*
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* %DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
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* Lowest VPU virtual address available in the current context (read-only)
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*
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* %DRM_IVPU_PARAM_CONTEXT_PRIORITY:
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* Value of current context scheduling priority (read-write).
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* See DRM_IVPU_CONTEXT_PRIORITY_* for possible values.
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*
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* %DRM_IVPU_PARAM_CONTEXT_ID:
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* Current context ID, always greater than 0 (read-only)
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*
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* %DRM_IVPU_PARAM_FW_API_VERSION:
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* Firmware API version array (read-only)
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*
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* %DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
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* Heartbeat value from an engine (read-only).
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* Engine ID (i.e. DRM_IVPU_ENGINE_COMPUTE) is given via index.
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*
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* %DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
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* Device-unique inference ID (read-only)
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*
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* %DRM_IVPU_PARAM_TILE_CONFIG:
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* VPU tile configuration (read-only)
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*
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* %DRM_IVPU_PARAM_SKU:
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* VPU SKU ID (read-only)
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*
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*/
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__u32 param;
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/** @index: Index for params that have multiple instances */
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__u32 index;
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/** @value: Param value */
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__u64 value;
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};
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#define DRM_IVPU_BO_HIGH_MEM 0x00000001
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#define DRM_IVPU_BO_MAPPABLE 0x00000002
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#define DRM_IVPU_BO_CACHED 0x00000000
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#define DRM_IVPU_BO_UNCACHED 0x00010000
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#define DRM_IVPU_BO_WC 0x00020000
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#define DRM_IVPU_BO_CACHE_MASK 0x00030000
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#define DRM_IVPU_BO_FLAGS \
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(DRM_IVPU_BO_HIGH_MEM | \
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DRM_IVPU_BO_MAPPABLE | \
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DRM_IVPU_BO_CACHE_MASK)
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/**
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* struct drm_ivpu_bo_create - Create BO backed by SHMEM
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*
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* Create GEM buffer object allocated in SHMEM memory.
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*/
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struct drm_ivpu_bo_create {
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/** @size: The size in bytes of the allocated memory */
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__u64 size;
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/**
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* @flags:
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*
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* Supported flags:
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*
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* %DRM_IVPU_BO_HIGH_MEM:
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*
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* Allocate VPU address from >4GB range.
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* Buffer object with vpu address >4GB can be always accessed by the
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* VPU DMA engine, but some HW generation may not be able to access
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* this memory from then firmware running on the VPU management processor.
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* Suitable for input, output and some scratch buffers.
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*
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* %DRM_IVPU_BO_MAPPABLE:
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*
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* Buffer object can be mapped using mmap().
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*
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* %DRM_IVPU_BO_CACHED:
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*
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* Allocated BO will be cached on host side (WB) and snooped on the VPU side.
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* This is the default caching mode.
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*
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* %DRM_IVPU_BO_UNCACHED:
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*
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* Allocated BO will not be cached on host side nor snooped on the VPU side.
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*
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* %DRM_IVPU_BO_WC:
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*
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* Allocated BO will use write combining buffer for writes but reads will be
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* uncached.
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*/
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__u32 flags;
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/** @handle: Returned GEM object handle */
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__u32 handle;
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/** @vpu_addr: Returned VPU virtual address */
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__u64 vpu_addr;
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};
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/**
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* struct drm_ivpu_bo_info - Query buffer object info
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*/
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struct drm_ivpu_bo_info {
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/** @handle: Handle of the queried BO */
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__u32 handle;
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/** @flags: Returned flags used to create the BO */
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__u32 flags;
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/** @vpu_addr: Returned VPU virtual address */
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__u64 vpu_addr;
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/**
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* @mmap_offset:
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*
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* Returned offset to be used in mmap(). 0 in case the BO is not mappable.
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*/
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__u64 mmap_offset;
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/** @size: Returned GEM object size, aligned to PAGE_SIZE */
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__u64 size;
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};
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/* drm_ivpu_submit engines */
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#define DRM_IVPU_ENGINE_COMPUTE 0
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#define DRM_IVPU_ENGINE_COPY 1
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/**
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* struct drm_ivpu_submit - Submit commands to the VPU
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*
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* Execute a single command buffer on a given VPU engine.
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* Handles to all referenced buffer objects have to be provided in @buffers_ptr.
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*
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* User space may wait on job completion using %DRM_IVPU_BO_WAIT ioctl.
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*/
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struct drm_ivpu_submit {
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/**
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* @buffers_ptr:
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*
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* A pointer to an u32 array of GEM handles of the BOs required for this job.
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* The number of elements in the array must be equal to the value given by @buffer_count.
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*
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* The first BO is the command buffer. The rest of array has to contain all
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* BOs referenced from the command buffer.
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*/
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__u64 buffers_ptr;
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/** @buffer_count: Number of elements in the @buffers_ptr */
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__u32 buffer_count;
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/**
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* @engine: Select the engine this job should be executed on
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*
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* %DRM_IVPU_ENGINE_COMPUTE:
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*
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* Performs Deep Learning Neural Compute Inference Operations
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*
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* %DRM_IVPU_ENGINE_COPY:
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*
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* Performs memory copy operations to/from system memory allocated for VPU
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*/
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__u32 engine;
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/** @flags: Reserved for future use - must be zero */
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__u32 flags;
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/**
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* @commands_offset:
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*
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* Offset inside the first buffer in @buffers_ptr containing commands
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* to be executed. The offset has to be 8-byte aligned.
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*/
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__u32 commands_offset;
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};
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/* drm_ivpu_bo_wait job status codes */
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#define DRM_IVPU_JOB_STATUS_SUCCESS 0
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/**
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* struct drm_ivpu_bo_wait - Wait for BO to become inactive
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*
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* Blocks until a given buffer object becomes inactive.
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* With @timeout_ms set to 0 returns immediately.
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*/
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struct drm_ivpu_bo_wait {
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/** @handle: Handle to the buffer object to be waited on */
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__u32 handle;
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/** @flags: Reserved for future use - must be zero */
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__u32 flags;
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/** @timeout_ns: Absolute timeout in nanoseconds (may be zero) */
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__s64 timeout_ns;
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/**
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* @job_status:
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*
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* Job status code which is updated after the job is completed.
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* &DRM_IVPU_JOB_STATUS_SUCCESS or device specific error otherwise.
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* Valid only if @handle points to a command buffer.
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*/
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__u32 job_status;
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/** @pad: Padding - must be zero */
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__u32 pad;
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};
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __UAPI_IVPU_DRM_H__ */
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