813 lines
20 KiB
YAML
813 lines
20 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek MT7530 and MT7531 Ethernet Switches
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maintainers:
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- Arınç ÜNAL <arinc.unal@arinc9.com>
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- Landen Chao <Landen.Chao@mediatek.com>
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- DENG Qingfang <dqfext@gmail.com>
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- Sean Wang <sean.wang@mediatek.com>
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- Daniel Golle <daniel@makrotopia.org>
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description: |
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There are three versions of MT7530, standalone, in a multi-chip module and
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built-into a SoC.
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MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
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MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs.
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The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four
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Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's
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memory map rather than using MDIO. The switch got an internally connected 10G
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CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs.
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MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs
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and the switch registers are directly mapped into SoC's memory map rather than
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using MDIO. The DSA driver currently doesn't support MT7620 variants.
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There is only the standalone version of MT7531.
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Port 5 on MT7530 has got various ways of configuration:
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- Port 5 can be used as a CPU port.
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- PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore,
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the gmac of the SoC which is wired to port 5 can connect to the PHY.
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This is usually used for connecting the wan port directly to the CPU to
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achieve 2 Gbps routing in total.
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The driver looks up the reg on the ethernet-phy node, which the phy-handle
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property on the gmac node refers to, to mux the specified phy.
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The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
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compatible string and the reg must be 1. So, for now, only gmac1 of a
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MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
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For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
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Check out example 5.
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- For the multi-chip module MT7530, in case of an external phy wired to
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gmac1 of the SoC, port 5 must not be enabled.
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In case of muxing PHY 0 or 4, the external phy must not be enabled.
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For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
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Check out example 6.
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- Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
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For the multi-chip module MT7530, the external phy must be wired TX to TX
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to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired
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this way.
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For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the
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external phy is connected TX to TX.
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For the MT7621 SoCs, rgmii2 group must be claimed with gpio function.
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Check out example 7.
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properties:
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compatible:
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oneOf:
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- description:
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Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC
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const: mediatek,mt7530
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- description:
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Standalone MT7531
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const: mediatek,mt7531
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- description:
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Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
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const: mediatek,mt7621
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- description:
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Built-in switch of the MT7988 SoC
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const: mediatek,mt7988-switch
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reg:
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maxItems: 1
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core-supply:
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description:
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Phandle to the regulator node necessary for the core power.
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"#gpio-cells":
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const: 2
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gpio-controller:
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type: boolean
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description: |
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If defined, LED controller of the MT7530 switch will run on GPIO mode.
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There are 15 controllable pins.
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port 0 LED 0..2 as GPIO 0..2
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port 1 LED 0..2 as GPIO 3..5
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port 2 LED 0..2 as GPIO 6..8
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port 3 LED 0..2 as GPIO 9..11
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port 4 LED 0..2 as GPIO 12..14
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"#interrupt-cells":
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const: 1
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interrupt-controller: true
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interrupts:
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maxItems: 1
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io-supply:
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description: |
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Phandle to the regulator node necessary for the I/O power.
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See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
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details for the regulator setup on these boards.
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mediatek,mcm:
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type: boolean
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description:
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Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530
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switch is a part of the multi-chip module.
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reset-gpios:
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description: |
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GPIO to reset the switch. Use this if mediatek,mcm is not used.
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This property is optional because some boards share the reset line with
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other components which makes it impossible to probe the switch if the
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reset line is used.
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maxItems: 1
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reset-names:
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const: mcm
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resets:
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description:
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Phandle pointing to the system reset controller with line index for the
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ethsys.
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maxItems: 1
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patternProperties:
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"^(ethernet-)?ports$":
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type: object
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patternProperties:
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"^(ethernet-)?port@[0-9]+$":
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type: object
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properties:
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reg:
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description:
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Port address described must be 5 or 6 for CPU port and from 0 to 5
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for user ports.
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allOf:
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- if:
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required: [ ethernet ]
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then:
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properties:
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reg:
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enum:
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- 5
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- 6
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required:
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- compatible
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- reg
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$defs:
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mt7530-dsa-port:
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patternProperties:
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"^(ethernet-)?ports$":
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patternProperties:
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"^(ethernet-)?port@[0-9]+$":
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if:
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required: [ ethernet ]
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then:
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if:
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properties:
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reg:
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const: 5
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then:
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properties:
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phy-mode:
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enum:
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- gmii
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- mii
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- rgmii
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else:
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properties:
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phy-mode:
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enum:
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- rgmii
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- trgmii
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mt7531-dsa-port:
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patternProperties:
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"^(ethernet-)?ports$":
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patternProperties:
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"^(ethernet-)?port@[0-9]+$":
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if:
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required: [ ethernet ]
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then:
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if:
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properties:
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reg:
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const: 5
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then:
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properties:
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phy-mode:
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enum:
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- 1000base-x
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- 2500base-x
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- rgmii
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- sgmii
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else:
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properties:
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phy-mode:
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enum:
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- 1000base-x
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- 2500base-x
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- sgmii
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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- if:
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required:
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- mediatek,mcm
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then:
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properties:
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reset-gpios: false
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required:
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- resets
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- reset-names
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- dependencies:
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interrupt-controller: [ interrupts ]
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- if:
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properties:
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compatible:
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const: mediatek,mt7530
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then:
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$ref: "#/$defs/mt7530-dsa-port"
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required:
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- core-supply
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- io-supply
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- if:
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properties:
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compatible:
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const: mediatek,mt7531
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then:
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$ref: "#/$defs/mt7531-dsa-port"
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properties:
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gpio-controller: false
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mediatek,mcm: false
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- if:
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properties:
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compatible:
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const: mediatek,mt7621
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then:
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$ref: "#/$defs/mt7530-dsa-port"
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required:
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- mediatek,mcm
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- if:
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properties:
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compatible:
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const: mediatek,mt7988-switch
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then:
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$ref: "#/$defs/mt7530-dsa-port"
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properties:
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gpio-controller: false
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mediatek,mcm: false
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reset-names: false
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unevaluatedProperties: false
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examples:
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# Example 1: Standalone MT7530
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "mediatek,mt7530";
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reg = <0x1f>;
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reset-gpios = <&pio 33 0>;
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core-supply = <&mt6323_vpa_reg>;
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io-supply = <&mt6323_vemc3v3_reg>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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# Example 2: MT7530 in MT7623AI SoC
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- |
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#include <dt-bindings/reset/mt2701-resets.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "mediatek,mt7530";
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reg = <0x1f>;
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mediatek,mcm;
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resets = <ðsys MT2701_ETHSYS_MCM_RST>;
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reset-names = "mcm";
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core-supply = <&mt6323_vpa_reg>;
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io-supply = <&mt6323_vemc3v3_reg>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "trgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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# Example 3: Standalone MT7531
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@0 {
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compatible = "mediatek,mt7531";
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reg = <0>;
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reset-gpios = <&pio 54 0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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# Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/reset/mt7621-reset.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "mediatek,mt7621";
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reg = <0x1f>;
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mediatek,mcm;
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resets = <&sysc MT7621_RST_MCM>;
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reset-names = "mcm";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "trgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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# Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/reset/mt7621-reset.h>
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii2_pins>;
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mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "rgmii";
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phy-handle = <&example5_ethphy4>;
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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/* MT7530's phy4 */
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example5_ethphy4: ethernet-phy@4 {
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reg = <4>;
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};
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switch@1f {
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compatible = "mediatek,mt7621";
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reg = <0x1f>;
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mediatek,mcm;
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resets = <&sysc MT7621_RST_MCM>;
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reset-names = "mcm";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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/* Commented out, phy4 is connected to gmac1.
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port@4 {
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reg = <4>;
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label = "wan";
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};
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*/
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port@6 {
|
||
reg = <6>;
|
||
ethernet = <&gmac0>;
|
||
phy-mode = "trgmii";
|
||
|
||
fixed-link {
|
||
speed = <1000>;
|
||
full-duplex;
|
||
pause;
|
||
};
|
||
};
|
||
};
|
||
};
|
||
};
|
||
};
|
||
|
||
# Example 6: MT7621: mux external phy to SoC's gmac1
|
||
- |
|
||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||
#include <dt-bindings/reset/mt7621-reset.h>
|
||
|
||
ethernet {
|
||
#address-cells = <1>;
|
||
#size-cells = <0>;
|
||
|
||
pinctrl-names = "default";
|
||
pinctrl-0 = <&rgmii2_pins>;
|
||
|
||
mac@1 {
|
||
compatible = "mediatek,eth-mac";
|
||
reg = <1>;
|
||
|
||
phy-mode = "rgmii";
|
||
phy-handle = <&example6_ethphy7>;
|
||
};
|
||
|
||
mdio {
|
||
#address-cells = <1>;
|
||
#size-cells = <0>;
|
||
|
||
/* External PHY */
|
||
example6_ethphy7: ethernet-phy@7 {
|
||
reg = <7>;
|
||
phy-mode = "rgmii";
|
||
};
|
||
|
||
switch@1f {
|
||
compatible = "mediatek,mt7621";
|
||
reg = <0x1f>;
|
||
|
||
mediatek,mcm;
|
||
resets = <&sysc MT7621_RST_MCM>;
|
||
reset-names = "mcm";
|
||
|
||
interrupt-controller;
|
||
#interrupt-cells = <1>;
|
||
interrupt-parent = <&gic>;
|
||
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
||
ethernet-ports {
|
||
#address-cells = <1>;
|
||
#size-cells = <0>;
|
||
|
||
port@0 {
|
||
reg = <0>;
|
||
label = "lan1";
|
||
};
|
||
|
||
port@1 {
|
||
reg = <1>;
|
||
label = "lan2";
|
||
};
|
||
|
||
port@2 {
|
||
reg = <2>;
|
||
label = "lan3";
|
||
};
|
||
|
||
port@3 {
|
||
reg = <3>;
|
||
label = "lan4";
|
||
};
|
||
|
||
port@4 {
|
||
reg = <4>;
|
||
label = "wan";
|
||
};
|
||
|
||
port@6 {
|
||
reg = <6>;
|
||
ethernet = <&gmac0>;
|
||
phy-mode = "trgmii";
|
||
|
||
fixed-link {
|
||
speed = <1000>;
|
||
full-duplex;
|
||
pause;
|
||
};
|
||
};
|
||
};
|
||
};
|
||
};
|
||
};
|
||
|
||
# Example 7: MT7621: mux external phy to MT7530's port 5
|
||
- |
|
||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||
#include <dt-bindings/reset/mt7621-reset.h>
|
||
|
||
ethernet {
|
||
#address-cells = <1>;
|
||
#size-cells = <0>;
|
||
|
||
pinctrl-names = "default";
|
||
pinctrl-0 = <&rgmii2_pins>;
|
||
|
||
mdio {
|
||
#address-cells = <1>;
|
||
#size-cells = <0>;
|
||
|
||
/* External PHY */
|
||
example7_ethphy7: ethernet-phy@7 {
|
||
reg = <7>;
|
||
phy-mode = "rgmii";
|
||
};
|
||
|
||
switch@1f {
|
||
compatible = "mediatek,mt7621";
|
||
reg = <0x1f>;
|
||
|
||
mediatek,mcm;
|
||
resets = <&sysc MT7621_RST_MCM>;
|
||
reset-names = "mcm";
|
||
|
||
interrupt-controller;
|
||
#interrupt-cells = <1>;
|
||
interrupt-parent = <&gic>;
|
||
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
||
ethernet-ports {
|
||
#address-cells = <1>;
|
||
#size-cells = <0>;
|
||
|
||
port@0 {
|
||
reg = <0>;
|
||
label = "lan1";
|
||
};
|
||
|
||
port@1 {
|
||
reg = <1>;
|
||
label = "lan2";
|
||
};
|
||
|
||
port@2 {
|
||
reg = <2>;
|
||
label = "lan3";
|
||
};
|
||
|
||
port@3 {
|
||
reg = <3>;
|
||
label = "lan4";
|
||
};
|
||
|
||
port@4 {
|
||
reg = <4>;
|
||
label = "wan";
|
||
};
|
||
|
||
port@5 {
|
||
reg = <5>;
|
||
label = "extphy";
|
||
phy-mode = "rgmii-txid";
|
||
phy-handle = <&example7_ethphy7>;
|
||
};
|
||
|
||
port@6 {
|
||
reg = <6>;
|
||
ethernet = <&gmac0>;
|
||
phy-mode = "trgmii";
|
||
|
||
fixed-link {
|
||
speed = <1000>;
|
||
full-duplex;
|
||
pause;
|
||
};
|
||
};
|
||
};
|
||
};
|
||
};
|
||
};
|