343 lines
10 KiB
C
343 lines
10 KiB
C
/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <nvif/class.h>
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static void
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gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80)));
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u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80)));
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const struct nvkm_enum *warp;
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char glob[128];
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nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
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warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
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nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: "
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"global %08x [%s] warp %04x [%s]\n",
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gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : "");
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr);
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}
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void
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gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
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{
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gv100_gr_trap_sm(gr, gpc, tpc, 0);
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gv100_gr_trap_sm(gr, gpc, tpc, 1);
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}
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void
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gv100_gr_init_4188a4(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000);
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}
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void
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gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int sm;
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for (sm = 0; sm < 0x100; sm += 0x80) {
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004);
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}
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}
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void
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gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000);
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}
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void
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gv100_gr_init_419bd8(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_mask(device, 0x419bd8, 0x00000700, 0x00000000);
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}
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u32
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gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc)
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{
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u32 pes, temp, tpc_new = 0;
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for (pes = 0; pes < gr->ppc_nr[gpc]; pes++) {
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if (gr->ppc_tpc_mask[gpc][pes] & BIT(tpc))
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break;
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tpc_new += gr->ppc_tpc_nr[gpc][pes];
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}
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temp = (BIT(tpc) - 1) & gr->ppc_tpc_mask[gpc][pes];
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temp = hweight32(temp);
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return tpc_new + temp;
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}
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static int
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gv100_gr_scg_estimate_perf(struct gf100_gr *gr, unsigned long *gpc_tpc_mask,
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u32 disable_gpc, u32 disable_tpc, int *perf)
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{
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const u32 scale_factor = 512UL; /* Use fx23.9 */
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const u32 pix_scale = 1024*1024UL; /* Pix perf in [29:20] */
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const u32 world_scale = 1024UL; /* World performance in [19:10] */
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const u32 tpc_scale = 1; /* TPC balancing in [9:0] */
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u32 scg_num_pes = 0;
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u32 min_scg_gpc_pix_perf = scale_factor; /* Init perf as maximum */
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u32 average_tpcs = 0; /* Average of # of TPCs per GPC */
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u32 deviation; /* absolute diff between TPC# and average_tpcs, averaged across GPCs */
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u32 norm_tpc_deviation; /* deviation/max_tpc_per_gpc */
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u32 tpc_balance;
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u32 scg_gpc_pix_perf;
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u32 scg_world_perf;
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u32 gpc;
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u32 pes;
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int diff;
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bool tpc_removed_gpc = false;
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bool tpc_removed_pes = false;
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u32 max_tpc_gpc = 0;
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u32 num_tpc_mask;
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u32 *num_tpc_gpc;
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int ret = -EINVAL;
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if (!(num_tpc_gpc = kcalloc(gr->gpc_nr, sizeof(*num_tpc_gpc), GFP_KERNEL)))
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return -ENOMEM;
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/* Calculate pix-perf-reduction-rate per GPC and find bottleneck TPC */
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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num_tpc_mask = gpc_tpc_mask[gpc];
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if ((gpc == disable_gpc) && num_tpc_mask & BIT(disable_tpc)) {
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/* Safety check if a TPC is removed twice */
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if (WARN_ON(tpc_removed_gpc))
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goto done;
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/* Remove logical TPC from set */
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num_tpc_mask &= ~BIT(disable_tpc);
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tpc_removed_gpc = true;
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}
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/* track balancing of tpcs across gpcs */
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num_tpc_gpc[gpc] = hweight32(num_tpc_mask);
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average_tpcs += num_tpc_gpc[gpc];
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/* save the maximum numer of gpcs */
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max_tpc_gpc = num_tpc_gpc[gpc] > max_tpc_gpc ? num_tpc_gpc[gpc] : max_tpc_gpc;
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/*
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* Calculate ratio between TPC count and post-FS and post-SCG
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*
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* ratio represents relative throughput of the GPC
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*/
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scg_gpc_pix_perf = scale_factor * num_tpc_gpc[gpc] / gr->tpc_nr[gpc];
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if (min_scg_gpc_pix_perf > scg_gpc_pix_perf)
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min_scg_gpc_pix_perf = scg_gpc_pix_perf;
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/* Calculate # of surviving PES */
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for (pes = 0; pes < gr->ppc_nr[gpc]; pes++) {
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/* Count the number of TPC on the set */
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num_tpc_mask = gr->ppc_tpc_mask[gpc][pes] & gpc_tpc_mask[gpc];
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if ((gpc == disable_gpc) && (num_tpc_mask & BIT(disable_tpc))) {
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if (WARN_ON(tpc_removed_pes))
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goto done;
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num_tpc_mask &= ~BIT(disable_tpc);
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tpc_removed_pes = true;
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}
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if (hweight32(num_tpc_mask))
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scg_num_pes++;
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}
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}
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if (WARN_ON(!tpc_removed_gpc || !tpc_removed_pes))
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goto done;
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if (max_tpc_gpc == 0) {
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*perf = 0;
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goto done_ok;
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}
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/* Now calculate perf */
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scg_world_perf = (scale_factor * scg_num_pes) / gr->ppc_total;
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deviation = 0;
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average_tpcs = scale_factor * average_tpcs / gr->gpc_nr;
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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diff = average_tpcs - scale_factor * num_tpc_gpc[gpc];
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if (diff < 0)
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diff = -diff;
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deviation += diff;
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}
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deviation /= gr->gpc_nr;
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norm_tpc_deviation = deviation / max_tpc_gpc;
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tpc_balance = scale_factor - norm_tpc_deviation;
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if ((tpc_balance > scale_factor) ||
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(scg_world_perf > scale_factor) ||
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(min_scg_gpc_pix_perf > scale_factor) ||
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(norm_tpc_deviation > scale_factor)) {
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WARN_ON(1);
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goto done;
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}
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*perf = (pix_scale * min_scg_gpc_pix_perf) +
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(world_scale * scg_world_perf) +
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(tpc_scale * tpc_balance);
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done_ok:
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ret = 0;
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done:
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kfree(num_tpc_gpc);
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return ret;
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}
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int
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gv100_gr_oneinit_sm_id(struct gf100_gr *gr)
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{
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unsigned long *gpc_tpc_mask;
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u32 *tpc_table, *gpc_table;
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u32 gpc, tpc, pes, gtpc;
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int perf, maxperf, ret = 0;
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gpc_tpc_mask = kcalloc(gr->gpc_nr, sizeof(*gpc_tpc_mask), GFP_KERNEL);
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gpc_table = kcalloc(gr->tpc_total, sizeof(*gpc_table), GFP_KERNEL);
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tpc_table = kcalloc(gr->tpc_total, sizeof(*tpc_table), GFP_KERNEL);
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if (!gpc_table || !tpc_table || !gpc_tpc_mask) {
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ret = -ENOMEM;
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goto done;
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}
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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for (pes = 0; pes < gr->ppc_nr[gpc]; pes++)
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gpc_tpc_mask[gpc] |= gr->ppc_tpc_mask[gpc][pes];
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}
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for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) {
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for (maxperf = -1, gpc = 0; gpc < gr->gpc_nr; gpc++) {
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for_each_set_bit(tpc, &gpc_tpc_mask[gpc], gr->tpc_nr[gpc]) {
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ret = gv100_gr_scg_estimate_perf(gr, gpc_tpc_mask, gpc, tpc, &perf);
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if (ret)
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goto done;
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/* nvgpu does ">=" here, but this gets us RM's numbers. */
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if (perf > maxperf) {
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maxperf = perf;
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gpc_table[gtpc] = gpc;
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tpc_table[gtpc] = tpc;
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}
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}
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}
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gpc_tpc_mask[gpc_table[gtpc]] &= ~BIT(tpc_table[gtpc]);
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}
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/*TODO: build table for sm_per_tpc != 1, don't use yet, but might need later? */
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for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) {
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gr->sm[gtpc].gpc = gpc_table[gtpc];
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gr->sm[gtpc].tpc = tpc_table[gtpc];
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gr->sm_nr++;
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}
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done:
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kfree(gpc_table);
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kfree(tpc_table);
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kfree(gpc_tpc_mask);
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return ret;
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}
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static const struct gf100_gr_func
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gv100_gr = {
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.oneinit_tiles = gm200_gr_oneinit_tiles,
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.oneinit_sm_id = gv100_gr_oneinit_sm_id,
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.init = gf100_gr_init,
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.init_419bd8 = gv100_gr_init_419bd8,
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.init_gpc_mmu = gm200_gr_init_gpc_mmu,
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.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
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.init_zcull = gf117_gr_init_zcull,
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.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
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.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
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.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
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.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
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.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
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.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.init_504430 = gv100_gr_init_504430,
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.init_shader_exceptions = gv100_gr_init_shader_exceptions,
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.init_rop_exceptions = gf100_gr_init_rop_exceptions,
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.init_exception2 = gf100_gr_init_exception2,
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.init_4188a4 = gv100_gr_init_4188a4,
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.trap_mp = gv100_gr_trap_mp,
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.fecs.reset = gf100_gr_fecs_reset,
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.rops = gm200_gr_rops,
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.gpc_nr = 6,
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.tpc_nr = 7,
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.ppc_nr = 3,
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.grctx = &gv100_grctx,
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.zbc = &gp102_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, VOLTA_A, &gf100_fermi },
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{ -1, -1, VOLTA_COMPUTE_A },
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{}
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}
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};
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MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin");
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static const struct gf100_gr_fwif
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gv100_gr_fwif[] = {
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{ 0, gm200_gr_load, &gv100_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
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{ -1, gm200_gr_nofw },
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{}
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};
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int
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gv100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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return gf100_gr_new_(gv100_gr_fwif, device, type, inst, pgr);
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}
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