142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is part of wl1271
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*
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* Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*/
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#ifndef __RX_H__
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#define __RX_H__
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#include <linux/bitops.h>
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#define WL1271_RX_MAX_RSSI -30
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#define WL1271_RX_MIN_RSSI -95
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#define RSSI_LEVEL_BITMASK 0x7F
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#define ANT_DIVERSITY_BITMASK BIT(7)
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#define SHORT_PREAMBLE_BIT BIT(0)
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#define OFDM_RATE_BIT BIT(6)
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#define PBCC_RATE_BIT BIT(7)
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#define PLCP_HEADER_LENGTH 8
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#define RX_DESC_PACKETID_SHIFT 11
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#define RX_MAX_PACKET_ID 3
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#define RX_DESC_VALID_FCS 0x0001
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#define RX_DESC_MATCH_RXADDR1 0x0002
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#define RX_DESC_MCAST 0x0004
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#define RX_DESC_STAINTIM 0x0008
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#define RX_DESC_VIRTUAL_BM 0x0010
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#define RX_DESC_BCAST 0x0020
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#define RX_DESC_MATCH_SSID 0x0040
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#define RX_DESC_MATCH_BSSID 0x0080
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#define RX_DESC_ENCRYPTION_MASK 0x0300
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#define RX_DESC_MEASURMENT 0x0400
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#define RX_DESC_SEQNUM_MASK 0x1800
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#define RX_DESC_MIC_FAIL 0x2000
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#define RX_DESC_DECRYPT_FAIL 0x4000
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/*
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* RX Descriptor flags:
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*
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* Bits 0-1 - band
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* Bit 2 - STBC
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* Bit 3 - A-MPDU
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* Bit 4 - HT
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* Bits 5-7 - encryption
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*/
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#define WL1271_RX_DESC_BAND_MASK 0x03
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#define WL1271_RX_DESC_ENCRYPT_MASK 0xE0
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#define WL1271_RX_DESC_BAND_BG 0x00
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#define WL1271_RX_DESC_BAND_J 0x01
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#define WL1271_RX_DESC_BAND_A 0x02
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#define WL1271_RX_DESC_STBC BIT(2)
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#define WL1271_RX_DESC_A_MPDU BIT(3)
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#define WL1271_RX_DESC_HT BIT(4)
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#define WL1271_RX_DESC_ENCRYPT_WEP 0x20
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#define WL1271_RX_DESC_ENCRYPT_TKIP 0x40
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#define WL1271_RX_DESC_ENCRYPT_AES 0x60
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#define WL1271_RX_DESC_ENCRYPT_GEM 0x80
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/*
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* RX Descriptor status
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*
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* Bits 0-2 - error code
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* Bits 3-5 - process_id tag (AP mode FW)
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* Bits 6-7 - reserved
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*/
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#define WL1271_RX_DESC_STATUS_MASK 0x07
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#define WL1271_RX_DESC_SUCCESS 0x00
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#define WL1271_RX_DESC_DECRYPT_FAIL 0x01
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#define WL1271_RX_DESC_MIC_FAIL 0x02
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#define RX_MEM_BLOCK_MASK 0xFF
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#define RX_BUF_SIZE_MASK 0xFFF00
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#define RX_BUF_SIZE_SHIFT_DIV 6
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#define ALIGNED_RX_BUF_SIZE_MASK 0xFFFF00
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#define ALIGNED_RX_BUF_SIZE_SHIFT 8
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/* If set, the start of IP payload is not 4 bytes aligned */
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#define RX_BUF_UNALIGNED_PAYLOAD BIT(20)
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/* If set, the buffer was padded by the FW to be 4 bytes aligned */
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#define RX_BUF_PADDED_PAYLOAD BIT(30)
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/*
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* Account for the padding inserted by the FW in case of RX_ALIGNMENT
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* or for fixing alignment in case the packet wasn't aligned.
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*/
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#define RX_BUF_ALIGN 2
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/* Describes the alignment state of a Rx buffer */
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enum wl_rx_buf_align {
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WLCORE_RX_BUF_ALIGNED,
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WLCORE_RX_BUF_UNALIGNED,
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WLCORE_RX_BUF_PADDED,
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};
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enum {
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WL12XX_RX_CLASS_UNKNOWN,
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WL12XX_RX_CLASS_MANAGEMENT,
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WL12XX_RX_CLASS_DATA,
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WL12XX_RX_CLASS_QOS_DATA,
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WL12XX_RX_CLASS_BCN_PRBRSP,
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WL12XX_RX_CLASS_EAPOL,
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WL12XX_RX_CLASS_BA_EVENT,
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WL12XX_RX_CLASS_AMSDU,
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WL12XX_RX_CLASS_LOGGER,
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};
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struct wl1271_rx_descriptor {
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__le16 length;
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u8 status;
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u8 flags;
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u8 rate;
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u8 channel;
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s8 rssi;
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u8 snr;
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__le32 timestamp;
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u8 packet_class;
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u8 hlid;
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u8 pad_len;
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u8 reserved;
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} __packed;
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int wlcore_rx(struct wl1271 *wl, struct wl_fw_status *status);
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u8 wl1271_rate_to_idx(int rate, enum nl80211_band band);
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int wl1271_rx_filter_enable(struct wl1271 *wl,
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int index, bool enable,
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struct wl12xx_rx_filter *filter);
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int wl1271_rx_filter_clear_all(struct wl1271 *wl);
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#endif
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