680 lines
17 KiB
C
680 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/delay.h>
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#include "nitrox_dev.h"
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#include "nitrox_csr.h"
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#include "nitrox_hal.h"
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#define PLL_REF_CLK 50
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#define MAX_CSR_RETRIES 10
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/**
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* emu_enable_cores - Enable EMU cluster cores.
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* @ndev: NITROX device
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*/
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static void emu_enable_cores(struct nitrox_device *ndev)
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{
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union emu_se_enable emu_se;
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union emu_ae_enable emu_ae;
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int i;
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/* AE cores 20 per cluster */
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emu_ae.value = 0;
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emu_ae.s.enable = 0xfffff;
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/* SE cores 16 per cluster */
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emu_se.value = 0;
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emu_se.s.enable = 0xffff;
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/* enable per cluster cores */
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for (i = 0; i < NR_CLUSTERS; i++) {
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nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);
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nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);
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}
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}
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/**
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* nitrox_config_emu_unit - configure EMU unit.
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* @ndev: NITROX device
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*/
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void nitrox_config_emu_unit(struct nitrox_device *ndev)
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{
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union emu_wd_int_ena_w1s emu_wd_int;
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union emu_ge_int_ena_w1s emu_ge_int;
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u64 offset;
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int i;
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/* enable cores */
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emu_enable_cores(ndev);
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/* enable general error and watch dog interrupts */
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emu_ge_int.value = 0;
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emu_ge_int.s.se_ge = 0xffff;
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emu_ge_int.s.ae_ge = 0xfffff;
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emu_wd_int.value = 0;
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emu_wd_int.s.se_wd = 1;
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for (i = 0; i < NR_CLUSTERS; i++) {
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offset = EMU_WD_INT_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, emu_wd_int.value);
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offset = EMU_GE_INT_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, emu_ge_int.value);
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}
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}
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static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
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{
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union nps_pkt_in_instr_ctl pkt_in_ctl;
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union nps_pkt_in_done_cnts pkt_in_cnts;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* step 1: disable the ring, clear enable bit */
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offset = NPS_PKT_IN_INSTR_CTLX(ring);
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_in_ctl.s.enb = 0;
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nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
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/* step 2: wait to clear [ENB] */
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usleep_range(100, 150);
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do {
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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if (!pkt_in_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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/* step 3: clear done counts */
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offset = NPS_PKT_IN_DONE_CNTSX(ring);
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pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
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usleep_range(50, 100);
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}
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void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
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{
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union nps_pkt_in_instr_ctl pkt_in_ctl;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* 64-byte instruction size */
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offset = NPS_PKT_IN_INSTR_CTLX(ring);
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_in_ctl.s.is64b = 1;
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pkt_in_ctl.s.enb = 1;
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nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
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/* wait for set [ENB] */
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do {
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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if (pkt_in_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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}
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/**
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* nitrox_config_pkt_input_rings - configure Packet Input Rings
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* @ndev: NITROX device
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*/
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void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
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{
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int i;
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for (i = 0; i < ndev->nr_queues; i++) {
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struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i];
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union nps_pkt_in_instr_rsize pkt_in_rsize;
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union nps_pkt_in_instr_baoff_dbell pkt_in_dbell;
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u64 offset;
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reset_pkt_input_ring(ndev, i);
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/**
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* step 4:
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* configure ring base address 16-byte aligned,
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* size and interrupt threshold.
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*/
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offset = NPS_PKT_IN_INSTR_BADDRX(i);
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nitrox_write_csr(ndev, offset, cmdq->dma);
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/* configure ring size */
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offset = NPS_PKT_IN_INSTR_RSIZEX(i);
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pkt_in_rsize.value = 0;
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pkt_in_rsize.s.rsize = ndev->qlen;
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nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
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/* set high threshold for pkt input ring interrupts */
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offset = NPS_PKT_IN_INT_LEVELSX(i);
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nitrox_write_csr(ndev, offset, 0xffffffff);
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/* step 5: clear off door bell counts */
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offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
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pkt_in_dbell.value = 0;
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pkt_in_dbell.s.dbell = 0xffffffff;
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nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
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/* enable the ring */
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enable_pkt_input_ring(ndev, i);
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}
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}
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static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_ctl pkt_slc_ctl;
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union nps_pkt_slc_cnts pkt_slc_cnts;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* step 1: disable slc port */
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offset = NPS_PKT_SLC_CTLX(port);
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_slc_ctl.s.enb = 0;
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nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
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/* step 2 */
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usleep_range(100, 150);
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/* wait to clear [ENB] */
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do {
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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if (!pkt_slc_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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/* step 3: clear slc counters */
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offset = NPS_PKT_SLC_CNTSX(port);
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pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
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usleep_range(50, 100);
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}
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void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_ctl pkt_slc_ctl;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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offset = NPS_PKT_SLC_CTLX(port);
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pkt_slc_ctl.value = 0;
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pkt_slc_ctl.s.enb = 1;
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/*
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* 8 trailing 0x00 bytes will be added
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* to the end of the outgoing packet.
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*/
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pkt_slc_ctl.s.z = 1;
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/* enable response header */
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pkt_slc_ctl.s.rh = 1;
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nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
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/* wait to set [ENB] */
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do {
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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if (pkt_slc_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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}
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static void config_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_int_levels pkt_slc_int;
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u64 offset;
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reset_pkt_solicit_port(ndev, port);
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/* step 4: configure interrupt levels */
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offset = NPS_PKT_SLC_INT_LEVELSX(port);
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pkt_slc_int.value = 0;
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/* time interrupt threshold */
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pkt_slc_int.s.timet = 0x3fffff;
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nitrox_write_csr(ndev, offset, pkt_slc_int.value);
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/* enable the solicit port */
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enable_pkt_solicit_port(ndev, port);
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}
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void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
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{
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int i;
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for (i = 0; i < ndev->nr_queues; i++)
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config_pkt_solicit_port(ndev, i);
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}
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/**
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* enable_nps_core_interrupts - enable NPS core interrutps
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* @ndev: NITROX device.
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*
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* This includes NPS core interrupts.
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*/
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static void enable_nps_core_interrupts(struct nitrox_device *ndev)
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{
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union nps_core_int_ena_w1s core_int;
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/* NPS core interrutps */
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core_int.value = 0;
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core_int.s.host_wr_err = 1;
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core_int.s.host_wr_timeout = 1;
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core_int.s.exec_wr_timeout = 1;
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core_int.s.npco_dma_malform = 1;
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core_int.s.host_nps_wr_err = 1;
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nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
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}
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void nitrox_config_nps_core_unit(struct nitrox_device *ndev)
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{
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union nps_core_gbl_vfcfg core_gbl_vfcfg;
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/* endian control information */
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nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL);
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/* disable ILK interface */
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core_gbl_vfcfg.value = 0;
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core_gbl_vfcfg.s.ilk_disable = 1;
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core_gbl_vfcfg.s.cfg = __NDEV_MODE_PF;
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nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
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/* enable nps core interrupts */
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enable_nps_core_interrupts(ndev);
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}
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/**
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* enable_nps_pkt_interrupts - enable NPS packet interrutps
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* @ndev: NITROX device.
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*
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* This includes NPS packet in and slc interrupts.
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*/
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static void enable_nps_pkt_interrupts(struct nitrox_device *ndev)
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{
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/* NPS packet in ring interrupts */
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
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/* NPS packet slc port interrupts */
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
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}
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void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev)
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{
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/* config input and solicit ports */
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nitrox_config_pkt_input_rings(ndev);
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nitrox_config_pkt_solicit_ports(ndev);
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/* enable nps packet interrupts */
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enable_nps_pkt_interrupts(ndev);
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}
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static void reset_aqm_ring(struct nitrox_device *ndev, int ring)
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{
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union aqmq_en aqmq_en_reg;
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union aqmq_activity_stat activity_stat;
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union aqmq_cmp_cnt cmp_cnt;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* step 1: disable the queue */
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offset = AQMQ_ENX(ring);
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aqmq_en_reg.value = 0;
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aqmq_en_reg.queue_enable = 0;
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nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
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/* step 2: wait for AQMQ_ACTIVITY_STATX[QUEUE_ACTIVE] to clear */
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usleep_range(100, 150);
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offset = AQMQ_ACTIVITY_STATX(ring);
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do {
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activity_stat.value = nitrox_read_csr(ndev, offset);
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if (!activity_stat.queue_active)
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break;
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udelay(50);
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} while (max_retries--);
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/* step 3: clear commands completed count */
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offset = AQMQ_CMP_CNTX(ring);
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cmp_cnt.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, cmp_cnt.value);
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usleep_range(50, 100);
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}
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void enable_aqm_ring(struct nitrox_device *ndev, int ring)
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{
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union aqmq_en aqmq_en_reg;
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u64 offset;
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offset = AQMQ_ENX(ring);
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aqmq_en_reg.value = 0;
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aqmq_en_reg.queue_enable = 1;
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nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
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usleep_range(50, 100);
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}
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void nitrox_config_aqm_rings(struct nitrox_device *ndev)
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{
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int ring;
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for (ring = 0; ring < ndev->nr_queues; ring++) {
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struct nitrox_cmdq *cmdq = ndev->aqmq[ring];
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union aqmq_drbl drbl;
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union aqmq_qsz qsize;
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union aqmq_cmp_thr cmp_thr;
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u64 offset;
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/* steps 1 - 3 */
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reset_aqm_ring(ndev, ring);
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/* step 4: clear doorbell count of ring */
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offset = AQMQ_DRBLX(ring);
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drbl.value = 0;
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drbl.dbell_count = 0xFFFFFFFF;
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nitrox_write_csr(ndev, offset, drbl.value);
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/* step 5: configure host ring details */
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/* set host address for next command of ring */
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offset = AQMQ_NXT_CMDX(ring);
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nitrox_write_csr(ndev, offset, 0ULL);
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/* set host address of ring base */
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offset = AQMQ_BADRX(ring);
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nitrox_write_csr(ndev, offset, cmdq->dma);
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/* set ring size */
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offset = AQMQ_QSZX(ring);
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qsize.value = 0;
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qsize.host_queue_size = ndev->qlen;
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nitrox_write_csr(ndev, offset, qsize.value);
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/* set command completion threshold */
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offset = AQMQ_CMP_THRX(ring);
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cmp_thr.value = 0;
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cmp_thr.commands_completed_threshold = 1;
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nitrox_write_csr(ndev, offset, cmp_thr.value);
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/* step 6: enable the queue */
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enable_aqm_ring(ndev, ring);
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}
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}
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static void enable_aqm_interrupts(struct nitrox_device *ndev)
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{
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/* clear interrupt enable bits */
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nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL));
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}
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void nitrox_config_aqm_unit(struct nitrox_device *ndev)
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{
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/* config aqm command queues */
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nitrox_config_aqm_rings(ndev);
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/* enable aqm interrupts */
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enable_aqm_interrupts(ndev);
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}
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void nitrox_config_pom_unit(struct nitrox_device *ndev)
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{
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union pom_int_ena_w1s pom_int;
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int i;
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/* enable pom interrupts */
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pom_int.value = 0;
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pom_int.s.illegal_dport = 1;
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nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);
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/* enable perf counters */
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for (i = 0; i < ndev->hw.se_cores; i++)
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nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));
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}
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/**
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* nitrox_config_rand_unit - enable NITROX random number unit
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* @ndev: NITROX device
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*/
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void nitrox_config_rand_unit(struct nitrox_device *ndev)
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{
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union efl_rnm_ctl_status efl_rnm_ctl;
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u64 offset;
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offset = EFL_RNM_CTL_STATUS;
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efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
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efl_rnm_ctl.s.ent_en = 1;
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efl_rnm_ctl.s.rng_en = 1;
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nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
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}
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void nitrox_config_efl_unit(struct nitrox_device *ndev)
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{
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int i;
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for (i = 0; i < NR_CLUSTERS; i++) {
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union efl_core_int_ena_w1s efl_core_int;
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u64 offset;
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/* EFL core interrupts */
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offset = EFL_CORE_INT_ENA_W1SX(i);
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efl_core_int.value = 0;
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efl_core_int.s.len_ovr = 1;
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efl_core_int.s.d_left = 1;
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efl_core_int.s.epci_decode_err = 1;
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nitrox_write_csr(ndev, offset, efl_core_int.value);
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offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, (~0ULL));
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offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, (~0ULL));
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}
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}
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void nitrox_config_bmi_unit(struct nitrox_device *ndev)
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{
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union bmi_ctl bmi_ctl;
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union bmi_int_ena_w1s bmi_int_ena;
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u64 offset;
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/* no threshold limits for PCIe */
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offset = BMI_CTL;
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bmi_ctl.value = nitrox_read_csr(ndev, offset);
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bmi_ctl.s.max_pkt_len = 0xff;
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bmi_ctl.s.nps_free_thrsh = 0xff;
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bmi_ctl.s.nps_hdrq_thrsh = 0x7a;
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nitrox_write_csr(ndev, offset, bmi_ctl.value);
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/* enable interrupts */
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offset = BMI_INT_ENA_W1S;
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bmi_int_ena.value = 0;
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bmi_int_ena.s.max_len_err_nps = 1;
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bmi_int_ena.s.pkt_rcv_err_nps = 1;
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bmi_int_ena.s.fpf_undrrn = 1;
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nitrox_write_csr(ndev, offset, bmi_int_ena.value);
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}
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|
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void nitrox_config_bmo_unit(struct nitrox_device *ndev)
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{
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union bmo_ctl2 bmo_ctl2;
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u64 offset;
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|
|
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/* no threshold limits for PCIe */
|
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offset = BMO_CTL2;
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bmo_ctl2.value = nitrox_read_csr(ndev, offset);
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bmo_ctl2.s.nps_slc_buf_thrsh = 0xff;
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nitrox_write_csr(ndev, offset, bmo_ctl2.value);
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}
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|
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void invalidate_lbc(struct nitrox_device *ndev)
|
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{
|
|
union lbc_inval_ctl lbc_ctl;
|
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union lbc_inval_status lbc_stat;
|
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int max_retries = MAX_CSR_RETRIES;
|
|
u64 offset;
|
|
|
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/* invalidate LBC */
|
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offset = LBC_INVAL_CTL;
|
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lbc_ctl.value = nitrox_read_csr(ndev, offset);
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lbc_ctl.s.cam_inval_start = 1;
|
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nitrox_write_csr(ndev, offset, lbc_ctl.value);
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|
|
|
offset = LBC_INVAL_STATUS;
|
|
do {
|
|
lbc_stat.value = nitrox_read_csr(ndev, offset);
|
|
if (lbc_stat.s.done)
|
|
break;
|
|
udelay(50);
|
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} while (max_retries--);
|
|
}
|
|
|
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void nitrox_config_lbc_unit(struct nitrox_device *ndev)
|
|
{
|
|
union lbc_int_ena_w1s lbc_int_ena;
|
|
u64 offset;
|
|
|
|
invalidate_lbc(ndev);
|
|
|
|
/* enable interrupts */
|
|
offset = LBC_INT_ENA_W1S;
|
|
lbc_int_ena.value = 0;
|
|
lbc_int_ena.s.dma_rd_err = 1;
|
|
lbc_int_ena.s.over_fetch_err = 1;
|
|
lbc_int_ena.s.cam_inval_abort = 1;
|
|
lbc_int_ena.s.cam_hard_err = 1;
|
|
nitrox_write_csr(ndev, offset, lbc_int_ena.value);
|
|
|
|
offset = LBC_PLM_VF1_64_INT_ENA_W1S;
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
|
offset = LBC_PLM_VF65_128_INT_ENA_W1S;
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
|
|
|
offset = LBC_ELM_VF1_64_INT_ENA_W1S;
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
|
offset = LBC_ELM_VF65_128_INT_ENA_W1S;
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
|
}
|
|
|
|
void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode)
|
|
{
|
|
union nps_core_gbl_vfcfg vfcfg;
|
|
|
|
vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG);
|
|
vfcfg.s.cfg = mode & 0x7;
|
|
|
|
nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);
|
|
}
|
|
|
|
static const char *get_core_option(u8 se_cores, u8 ae_cores)
|
|
{
|
|
const char *option = "";
|
|
|
|
if (ae_cores == AE_MAX_CORES) {
|
|
switch (se_cores) {
|
|
case SE_MAX_CORES:
|
|
option = "60";
|
|
break;
|
|
case 40:
|
|
option = "60s";
|
|
break;
|
|
}
|
|
} else if (ae_cores == (AE_MAX_CORES / 2)) {
|
|
option = "30";
|
|
} else {
|
|
option = "60i";
|
|
}
|
|
|
|
return option;
|
|
}
|
|
|
|
static const char *get_feature_option(u8 zip_cores, int core_freq)
|
|
{
|
|
if (zip_cores == 0)
|
|
return "";
|
|
else if (zip_cores < ZIP_MAX_CORES)
|
|
return "-C15";
|
|
|
|
if (core_freq >= 850)
|
|
return "-C45";
|
|
else if (core_freq >= 750)
|
|
return "-C35";
|
|
else if (core_freq >= 550)
|
|
return "-C25";
|
|
|
|
return "";
|
|
}
|
|
|
|
void nitrox_get_hwinfo(struct nitrox_device *ndev)
|
|
{
|
|
union emu_fuse_map emu_fuse;
|
|
union rst_boot rst_boot;
|
|
union fus_dat1 fus_dat1;
|
|
unsigned char name[IFNAMSIZ * 2] = {};
|
|
int i, dead_cores;
|
|
u64 offset;
|
|
|
|
/* get core frequency */
|
|
offset = RST_BOOT;
|
|
rst_boot.value = nitrox_read_csr(ndev, offset);
|
|
ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;
|
|
|
|
for (i = 0; i < NR_CLUSTERS; i++) {
|
|
offset = EMU_FUSE_MAPX(i);
|
|
emu_fuse.value = nitrox_read_csr(ndev, offset);
|
|
if (emu_fuse.s.valid) {
|
|
dead_cores = hweight32(emu_fuse.s.ae_fuse);
|
|
ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
|
|
dead_cores = hweight16(emu_fuse.s.se_fuse);
|
|
ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
|
|
}
|
|
}
|
|
/* find zip hardware availability */
|
|
offset = FUS_DAT1;
|
|
fus_dat1.value = nitrox_read_csr(ndev, offset);
|
|
if (!fus_dat1.nozip) {
|
|
dead_cores = hweight8(fus_dat1.zip_info);
|
|
ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores;
|
|
}
|
|
|
|
/* determine the partname
|
|
* CNN55<core option>-<freq><pincount>-<feature option>-<rev>
|
|
*/
|
|
snprintf(name, sizeof(name), "CNN55%s-%3dBG676%s-1.%u",
|
|
get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores),
|
|
ndev->hw.freq,
|
|
get_feature_option(ndev->hw.zip_cores, ndev->hw.freq),
|
|
ndev->hw.revision_id);
|
|
|
|
/* copy partname */
|
|
strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
|
|
}
|
|
|
|
void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
|
|
{
|
|
u64 value = ~0ULL;
|
|
u64 reg_addr;
|
|
|
|
/* Mailbox interrupt low enable set register */
|
|
reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1S;
|
|
nitrox_write_csr(ndev, reg_addr, value);
|
|
|
|
/* Mailbox interrupt high enable set register */
|
|
reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1S;
|
|
nitrox_write_csr(ndev, reg_addr, value);
|
|
}
|
|
|
|
void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
|
|
{
|
|
u64 value = ~0ULL;
|
|
u64 reg_addr;
|
|
|
|
/* Mailbox interrupt low enable clear register */
|
|
reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1C;
|
|
nitrox_write_csr(ndev, reg_addr, value);
|
|
|
|
/* Mailbox interrupt high enable clear register */
|
|
reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1C;
|
|
nitrox_write_csr(ndev, reg_addr, value);
|
|
}
|